SPEAR1310 datasheet(12/57 Pages) STMICROELECTRONICS

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CortexA9 subsystem (A9SM)

SPEAr1310

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Doc ID 17528 Rev 4

CortexA9 subsystem (A9SM)

The CPU subsystem is based on the ARM Cortex A9 processor, and has a dual core

configuration.

3.1

Main features

Each core has the following features:

●

ARM v7 CPU at 600 MHz

●

32 KB of L1 instruction CACHE with parity check

●

32 KB of L1 data CACHE with parity check

●

Embedded FPU for single and double data precision scalar floating-point operations

●

Memory management unit (MMU)

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ARM, Thumb2 and Thumb2-EE instruction set support

●

TrustZone© security extension

●

Program Trace Macrocell and CoreSight© component for software debug

●

JTAG interface

●

AMBA© 3 AXI 64-bit interface

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32-bit timer with 8-bit prescaler

●

Internal watchdog (working also as timer)

The dual core configuration is completed by a common set of components:

●

Snoop control unit (SCU) to manage inter-process communication, cache-2-cache and

system memory transfer, cache coherency

●

Generic interrupt control (GIC) unit configured to support 128 independent interrupt

sources with software configurable priority and routing between the two cores

●

64-bit global timer with 8-bit prescaler

●

Asynchronous accelerator coherency port (ACP)

●

Parity support to detect internal memory failures during runtime

●

512 KB of unified 8-way set associative L2 cache with support for parity check and

ECC

●

L2 Cache controller based on PL310 IP released by ARM

●

Dual 64-bit AMBA 3 AXI interface with possible filtering on the second one to use a

single port for DDR memory access

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