SPEAR1310 datasheet(27/57 Pages) STMICROELECTRONICS

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SPEAr1310

SATA gen-2 controller

Doc ID 17528 Rev 4

27/57

SATA gen-2 controller

The SATA AHCI Core implements the serial advanced technology attachment (SATA)

storage interface for physical storage devices.

14.1

Main features

This functional block supports the following features:

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SATA 3.0 Gb/s Gen II

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eSATA (external analog logic also needs to support eSATA)

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Compliant with the following specifications:

–

Serial ATA 3.0 (except FIS-based switching)

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AHCI Revision 1.3 (except FIS-based switching)

–

AMBA 3 AXI interfaces

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User-defined PHY status and control ports

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RX data buffer for recovered clock systems

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Data alignment circuitry when RX data buffer is also included

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OOB signaling detection and generation

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8b/10b encoding/decoding

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Asynchronous signal recovery, including retry polling

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Digital support of device hot-plugging

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Power management features including automatic partial-to-slumber transition

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BIST loopback modes

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Single SATA deviceInternal DMA engine per port

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Hardware-assisted native command queuing for up to 32 entries

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Port Multiplier with command-based switching

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Disabling RX and TX Data clocks during power down modes

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Integrated SATA link layer and transport layer logic

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Supports PIO, first party and legacy DMA modes

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Supports legacy command queuing

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Supports ATA and ATAPI master-only emulation mode (for instance, register and

command compatible with these standards)

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Power-down mode

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Data scrambling

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CRC computation

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Automatic data flow control

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Far end loop-back re-timed

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