SPEAR1340 datasheet(33/200 Pages) STMICROELECTRONICS

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SPEAr1340

Device functions

Doc ID 023063 Rev 4

33/200

A set of 16 general purpose registers (GP-Reg) are provided which can be used to save

data during the power down state. GP-Reg-set runs on 32 K oscillator clock and powered by

RTC battery. Each register is of 32 bits and addressed mapped on the 32-bit APB bus. A bit

in status register reflects the status of any pending write to GP-Reg-set. This means that

write operation to the GP-Reg-set should be sequential, so you should wait for this pending

status bit to be cleared before writing again to GP-Reg-set.

Main features:

●

Works on dedicated 32768 Hz external clock and power supply

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9999- year calendar

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Leap years support

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Programmable alarm interrupt

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Power management and self-isolation

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Prescaler and timer registers bypass for TEST

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Time and date update monitors

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16 general purpose registers which can be used to save data during power down state

2.31

DMA controllers (DMAC)

The SPEAr1340 device integrates 2 instances of a DMA controller (DMAC) digital block,

identified as DMAC0 and DMAC .

The DMAC is an AHB-central DMA controller core that transfers data from a source

peripheral to a destination peripheral over two AHB buses. A wrapper is designed to

instantiate 2 DMAC cores (each with 2 AHB master interfaces), 2 ICMs (which arbitrate the

same master interface of each DMAC) and a MUX (which manages multiple peripheral

handshaking interfaces).

Main features:

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AMBA 2.0-compliant

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AHB slave interface – used to program the DMAC

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8 channels, one per source and destination pair

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Unidirectional channels – data transfers in one direction only

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Programmable channel priority

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2 independent AHB master interfaces

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Data bus width configured to 64 bits for each AHB master interface

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Configurable endianness for master interfaces

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Support for memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral DMA transfers

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Component ID parameters for configurable software driver support

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Programmable source and destination addresses (on AHB bus)

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Address increment, decrement or no change

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Multiblock transfers achieved through linked lists (block chaining)

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Independent source and destination selection of multiblock transfer type

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Scatter/Gather

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