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AFE4490 Datenblatt(PDF) 39 Page - Texas Instruments

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Teilenummer AFE4490
Bauteilbeschribung  Integrated Analog Front-End for Pulse Oximeters
PDF  70 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

AFE4490 Datenblatt(HTML) 39 Page - Texas Instruments

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A7
A6
A1
A0
D23
D22
D17
D16
D15
D14
D9
D8
D7
D6
D1
D0
SPISTE
SPISIMO
SCLK
'RQ¶W FDUH, can be high or low.
AFE4490
www.ti.com
SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013
SERIAL PROGRAMMING INTERFACE
The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data
output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).
The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts
out data from the device. SCLK features a Schmitt-triggered input and clocks data out on SPISOMI. Data are
clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean
as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK
low.
The SPISOMI (SPI serial out master in) pin is used with SCLK to clock out the AFE4490 data. The SPISIMO
(SPI serial in master out) pin is used with SCLK to clock in data to the AFE4490. The SPISTE (SPI serial
interface enable) pin enables the serial interface to clock data on the SPISIMO pin in to the device.
READING AND WRITING DATA
The device has a set of internal registers that can be accessed by the serial programming interface formed by
the SPISTE, SCLK, SPISIMO, and SPISOMI pins.
Writing Data
When SPISTE is low,
Serially shifting bits into the device is enabled.
Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
The serial data are loaded into the register at every 32nd SCLK rising edge.
In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in
multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and
the remaining 24 bits form the register data. Figure 51 shows a diagram of the write timing.
Figure 51. AFE SPI Write Timing Diagram
Copyright © 2012–2013, Texas Instruments Incorporated
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