AFE4490 datasheet(27/70 Pages) TI

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ADC Clock

ADC Convert

LED2 Data

ADC Output Rate

PRF Samples per Second

ADC

Ambient

(LED2) Data

LED1 Data

Ambient

(LED1) Data

Rx Digital

Averager

Number of Averages

22-Bits

LED2 Data

LED2_Ambient Data

LED1 Data

LED1_Ambient Data

ADC Reset

AFE4490

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SBAS602B – DECEMBER 2012 – REVISED FEBRUARY 2013

ADC OPERATION AND AVERAGING MODULE

The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%,

and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts. Each ADC

conversion takes 50 µs.

There are two modes of operation: without averaging and with averaging. The averaging mode can average

multiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usually

shorter than 25% of the pulse repetition period. Figure 37 shows a diagram of the averaging module.

Figure 37. Averaging Module

Operation Without Averaging

In this mode, the ADC outputs a digital sample one time for every 50 µs. At the next rising edge of the ADC reset

signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 38):

•

At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.

•

At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.

•

At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch.

•

At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers

2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register

2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

Operation With Averaging

In this mode, all ADC digital samples are accumulated and averaged after every 50 µs. At the next rising edge of

the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see

Figure 39):

•

At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.

•

At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.

•

At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.

•

At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah

and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.

At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.

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