DAC8143

–11–

REV. C

ANALOG/DIGITAL DIVISION

The transfer function for the DAC8143 connect in the multiply-

ing mode as shown in Figures 16 and 17 is:

+

+

+ ...









“OFF” bit.

The transfer function is modified when the DAC is connected in

the feedback of an operational amplifier as shown in Figure 20

and is:

+

+

+ ...





















The above transfer function is the division of an analog voltage

bits “OFF” since division by zero is infinity. With all bits “ON”

the gain is 1 (

±1 LSB). The gain becomes 4096 with the LSB,

Bit 12, “ON”.

BUFFERED DIGITAL

DATA OUT

+5V

SRO

DAC8143

AGND

DGND

32 12

15

6

14

16

1

3

2

6

413

DIGITAL

INPUTS

OP-42

+

–

Figure 20. Analog/Digital Divider

APPLICATION TIPS

other. In most applications, the DAC is connected to an exter-

nal op amp with its noninverting input tied to ground (see Fig-

ures 16 and 17). The amplifier selected should have a low input

bias current and low drift over temperature. The amplifier’s

input offset voltage should be nulled to less than

±200 µV (less

than 10% of 1 LSB).

The operational amplifier’s noninverting input should have a

minimum resistance connection to ground; the usual bias cur-

rent compensation resistor should not be used. This resistor can

cause a variable offset voltage appearing as a varying output

error. All grounded pins should tie to a single common ground

have a low noise level with no transients greater than +17 V.

It is recommended that the digital inputs be taken to ground or

mulation of static charge if the PC card is disconnected from the

system.

Peak supply current flows as the digital input pass through the

transition region (see Figure 4). The supply current decreases as

i.e., rapidly slewing logic signals that settle very near the supply

rails will minimize supply current.

INTERFACING TO THE MC6800

As shown in Figure 21, the DAC8143 may be interfaced to the

6800 by successively executing memory WRITE instruction

while manipulating the data between WRITEs, so that each

WRITE presents the next bit.

In this example, the most significant bits are found in memory

locations 0000 and 0001. The four MSBs are found in the lower

half of 0000, the eight LSBs in 0001. The data is taken from the

a decoded memory WRITE to a memory location, R/

W, and

Φ2. A WRITE to another address location transfers data from

input register to DAC register.

DAC8143*

SRI

SRO

CLR

74LS138

ADDRESS

DECODER

R/

W

MC6800

16-BIT ADDRESS BUS

8-BIT DATA BUS

+5V

FROM SYSTEM RESET

φ2

Figure 21. DAC8143—MC6800 Interface

ADDRESS

DECODER

STROBE

LOAD

DAC8143

SRI

SRO

ADDRESS BUS

STROBE

LOAD

DAC8143

SRI

SRO

STROBE

LOAD

DAC8143

SRI

SRO

STROBE

LOAD

DAC8143

SRI

SRO

P

WR

Figure 19. Multiple DAC8143s with Three-Wire Interface