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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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DAC8412BTC/883 Datenblatt(PDF) 3 Page - Analog Devices |
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DAC8412BTC/883 Datenblatt(HTML) 3 Page - Analog Devices |
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3 / 14 page  –3– REV. D DAC8412/DAC8413 (@ VDD = VLOGIC = +5.0 V 5%, VSS = 0.0 V, VREFH = +2.5 V, VREFL = 0.0 V, and VSS = –5.0 V 5%, VREFL = –2.5 V, –40 C ≤ TA ≤ +85 C unless otherwise noted. See Note 1 for supply variations.) ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Units Integral Nonlinearity Error INL E Grade 1/2 ±1 LSB INL F Grade ±2 LSB INL VSS = 0.0 V; E Grade 2 ±2 LSB INL VSS = 0.0 V; F Grade 2 ±4 LSB Differential Nonlinearity Error DNL Monotonic Over Temperature –1 LSB Min-Scale Error VZSE VSS = –5.0 V ±4 LSB Full-Scale Error VFSE VSS = –5.0 V ±4 LSB Min-Scale Error VZSE VSS = 0.0 V ±8 LSB Full-Scale Error VFSE VSS = 0.0 V ±8 LSB Min-Scale Tempco TCVZSE 100 ppm/ °C Full-Scale Tempco TCVFSE 100 ppm/ °C Linearity Matching Adjacent DAC Matching ±1 LSB REFERENCE Positive Reference Input Voltage Range Note 3 VREFL + 2.5 VDD – 2.5 V Negative Reference Input Voltage Range VSS = 0.0 V 0 VREFH – 2.5 V VSS = –5.0 V –2.5 VREFH – 2.5 V Reference High Input Current IREFH Code 000H –1.0 +1.0 mA Large Signal Bandwidth BW –3 dB, VREFH = 0 V to 2.5 V p-p 450 kHz AMPLIFIER CHARACTERISTICS Output Current IOUT RL = 2 k Ω, C L = 100 pF –1.25 +1.25 mA Settling Time tS to 0.01%, 2.5 V Step, RL = 1 k Ω 7 µs Slew Rate SR 10% to 90% 2.2 V/ µs LOGIC CHARACTERISTICS Logic Input High Voltage VINH TA = +25 °C2.4 V Logic Input Low Voltage VINL TA = +25 °C0.8 V Logic Output High Voltage VOH IOH = +0.4 mA 2.4 V Logic Output Low Voltage VOL IOL = –1.6 mA 0.45 V Logic Input Current IIN 1 µA Input Capacitance CIN 8pF LOGIC TIMING CHARACTERISTICS 4 Note 5 Chip Select Write Pulsewidth tWCS 150 ns Write Setup tWS tWCS = 150 ns 0 ns Write Hold tWH tWCS = 150 ns 0 ns Address Setup tAS 0ns Address Hold tAH 0ns Load Setup tLS 70 ns Load Hold tLH 50 ns Write Data Setup tWDS tWCS = 150 ns 20 ns Write Data Hold tWDH tWCS = 150 ns 0 ns Load Data Pulsewidth tLDW 180 ns Reset Pulsewidth tRESET 150 ns Chip Select Read Pulsewidth tRCS 170 ns Read Data Hold tRDH tRCS = 170 ns 20 ns Read Data Setup tRDS tRCS = 170 ns 0 ns Data to Hi Z tDZ CL = 10 pF 200 ns Chip Select to Data tCSD CL = 100 pF 320 ns SUPPLY CHARACTERISTICS Power Supply Sensitivity PSS 100 ppm/V Positive Supply Current IDD 712 mA Negative Supply Current ISS VSS = –5.0 V –10 mA Power Dissipation PDISS VSS = 0 V 60 mW VSS = –5 V 110 mW NOTES 1All supplies can be varied ±5%, and operation is guaranteed. Device is tested with V DD = +4.75 V. 2For single supply operation only (V REFL = 0.0 V, VSS = 0.0 V): Due to internal offset errors, INL and DNL are measured beginning at code 2 (002 H). 3Operation is guaranteed over this reference range, but linearity is neither tested nor guaranteed. 4All parameters are guaranteed by design. 5All input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. Specifications subject to change without notice. |
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