DAC8412/DAC8413

–10–

REV. D

10000

1

1000

100

10

10.0

NOISE FREQUENCY – Hz

0.10

0.001

1.00

0.01

Figure 29. DAC8412 Noise

Frequency vs. Noise Density

0

0

25

–20

–30

–25 –20

0

–10

10

20

30

20

15

10

5

0

–5

–10

–15

CH1 MEAN

66.19 V

M 200 s

A CH1

12.9mV

20uV/DIV

1

Figure 31. Broadband Noise

OPERATION

Introduction

The DAC8412 and DAC8413 are quad, voltage output, 12-bit

parallel input DACs featuring a 12-bit data bus with readback

capability. The only differences between the DAC8412 and

DAC8413 are the reset functions. The DAC8412 resets to mid-

The ability to operate from a single +5 V supply is a unique fea-

ture of these DACs.

Operation of the DAC8412 and DAC8413 can be viewed by

dividing the system into three separate functional groups: the

digital I/O and logic, the digital to analog converters and the output

amplifiers.

DACs

Each DAC is a voltage switched, high impedance (R = 50 k

Ω),

R-2R ladder configuration. Each 2R resistor is driven by a pair of

Glitch

Worst-case glitch occurs at the transition between half-scale

digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111

1111 1111. It can be measured at about 2 V

µs. (See Figure 33.)

For demanding applications such as waveform generation or

precision instrumentation control, a deglitcher circuit can be

implemented with a standard sample-and-hold circuit. (See

Figure 34.) When

CS is enabled by synchronizing the hold

period to be longer than the glitch tradition, the output voltage

can be smoothed with minimum disturbance. A quad sample-

and-hold amplifier, SMP04, has been used to illustrate the

deglitching result. (See Figure 33.)

HS

H

S

S/H

CS

DACOUT'

DACOUT

DACOUT

DACOUT'

S/H

Figure 34. Deglitcher Circuit

6

–6

5

25

15

–5

–15

–25

20

10

0

–10

–20

–4

–20

2

4

4 s

1V

1V

GLITCH AT DAC OUTPUT

DEGLITCHER OUTPUT

CH2

1.86V

2

1

10 s

Figure 33. Glitch and Deglitched Results