SCL

S

P

P

STO

condition

SDA

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LM3565

www.ti.com

SNVS957 – JANUARY 2013

I

Data Validity

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state

of the data line can only be changed when CLK is LOW.

Figure 48. Data Validity Diagram

on SDA. Using a larger pullup resistor results in lower switching current with slower edges, while using a smaller

pull-up results in higher switching currents with faster edges.

Start and Stop Conditions

condition is defined as SDA signal transitioning from HIGH to LOW while SCL line is HIGH. A STOP condition is

repeated START conditions. First START and repeated START conditions are equivalent, function-wise. The

data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state of

the data line can only be changed when CLK is LOW.

Figure 49. Start and Stop Conditions

Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LM3565 pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The LM3565 generates an

acknowledge after each byte has been received.

followed by an eighth bit which is a data direction bit (R/W). The LM3565 address is 30h. For the eighth bit, a '0'

indicates a WRITE and a '1' indicates a READ. The second byte selects the register to which the data will be

written. The third byte contains data to write to the selected register.

Copyright © 2013, Texas Instruments Incorporated

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