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LM3565 Datenblatt(PDF) 20 Page - Texas Instruments |
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LM3565 Datenblatt(HTML) 20 Page - Texas Instruments |
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20 / 35 page ![]() TXEN TXR3 TXR2 TXR1 TXR0 ICL1 ICL0 ETEN Tx-Mask Register Address: 0x03 Default: 0 1 1 1 1 0 1 1 Definition: LM3565 SNVS957 – JANUARY 2013 www.ti.com TXEN: TX-Mask Enable Bit. '0' = TX-Mask Disabled. '1' = TX-Mask Enabled. TXR3-TXR0: TX-Mask Current Reduction Bits. See TX-Mask Flash Current Reduction Levels table. ICL1-ICL0: Inductor Peak Current Limit Bits. See Peak Inductor Current Limit Levels table. ETEN: External Torch Enable Bit. '0' = External Torch Mode disabled in standby. '1' = External Torch Mode allowed/enabled in standby. Table 3. TX-Mask Flash Current Reduction Levels Flash Reduction TXR3 TXR2 TXR1 TXR0 Level 0 0 0 0 30 mA 0 0 0 1 60 mA 0 0 1 0 90 mA 0 0 1 1 120 mA 0 1 0 0 150 mA 0 1 0 1 180 mA 0 1 1 0 210 mA 0 1 1 1 240 mA 1 0 0 0 270 mA 1 0 0 1 300 mA 1 0 1 0 330 mA 1 0 1 1 360 mA 1 1 0 0 390 mA 1 1 0 1 420 mA 1 1 1 0 450 mA 1 1 1 1 480 mA Table 4. Peak Inductor Current Limit Levels ICL1 ICL0 Peak Inductor Current Limit 0 0 2.3A 0 1 2.6A 1 0 2.9A 1 1 3.3A 20 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: LM3565 |
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