SPEAR320-2 datasheet(9/73 Pages) STMICROELECTRONICS

9 / 73 page

SPEAr320

Main features

Doc ID 16755 Rev 5

9/73

Main features

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ARM926EJ-S 32-bit RISC CPU, up to 333 MHz

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16 Kbytes of instruction cache, 16 Kbytes of data cache

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3 instruction sets: 32-bit for high performance, 16-bit (Thumb) for efficient code

density, byte Java mode (Jazelle™) for direct execution of Java code.

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Tightly Coupled Memory

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32-KByte on-chip BootROM

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8-KByte on-chip SRAM

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External DRAM memory interface:

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8/16-bit (mobile DDR@166 MHz)

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8/16-bit (DDR2@333 MHz)

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Serial memory interface

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SDIO interface supporting SPI, SD1, SFD4 and SD8 modes

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8/16-bits NAND Flash controller (FSMC)

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External memory interface (EMI) for connecting NOR Flash or FPGAs

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Boot capability from NAND Flash, serial/parallel NOR Flash

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Boot and field upgrade capability from USB

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High performance 8-channel DMA controller

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3x Ethernet controllers (up to 2 operating concurrently)

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Two USB2.0 Host (high-full-low speed) with integrated PHY transceiver

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One USB2.0 Device (high-full-low speed) with integrated PHY transceiver

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2x CAN 2.0 interfaces

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Up to 102 GPIOs with interrupt capability

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Up to 4 PWM outputs

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3x SSP master/slave (supporting Motorola, Texas instruments, National semiconductor

protocols) up to 41.5 Mbps

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Standard parallel port (SPP device implementation)

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2 x I2C master/slave interface (slow-fast-high speed, up to 1.2 Mb/s)

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3x UART:

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UART0 (up to 3 Mbps) with hardware flow control and modem interface

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UART1 (up to 7 Mbps) with hardware flow control (in some operating modes)

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UART2 (up to 7 Mbps) with software flow control

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ADC 10-bit, 1 Msps 8 inputs

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JPEG CODEC accelerator 1 clock/pixel

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Color LCD interface (up to 1024X768, 24-bits CLCD controller, TFT and STN panels)

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Touchscreen support

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Crypto accelerator (DES/3DES/AES/SHA1)

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