SPEAR320-2 datasheet(16/73 Pages) STMICROELECTRONICS

16 / 73 page

Architecture overview

SPEAr320

16/73

Doc ID 16755 Rev 5

3.9.1

MII0 Ethernet controller

Main features:

●

Supports the default Media Independent Interface (MII) defined in the IEEE 802.3

specifications.

●

Supports 10/100 Mbps data transfer rates

●

Local FIFO available (4 Kbyte RX, 2 Kbyte TX)

●

Supports both half-duplex and full-duplex operation. In half-duplex operation,

CSMA/CD protocol is provided

●

Programmable frame length to support both standard and jumbo Ethernet frames with

size up to 16 Kbytes

●

32/64/128-bit data transfer interface on system-side.

●

A variety of flexible address filtering modes are supported

●

A set of control and status registers (CSRs) to control GMAC core operation

●

Native DMA with single-channel transmit and receive engines, providing 32/64/128-bit

data transfers

●

DMA implements dual-buffer (ring) or linked-list (chained) descriptor chaining

●

An AHB slave acting as programming interface to access all CSRs, for both DMA and

GMAC core subsystems

●

An AHB master for data transfer to system memory

●

32-bit AHB master bus width, supporting 32, 64, and 128-bit wide data transactions

●

It supports both big-endian and little-endian.

3.9.2

SMII0/SMII1/MII1 Ethernet controllers

The two Ethernet controllers called SMII0 and SMII1/MII1 each have dedicated TX/RX

signals while synchronization and clock signals are common for PHY connection.

Each of the two ports provides the following features:

●

Compatible with IEEE Standard 802.3

●

10 and 100 Mbit/s operation

●

Full and half duplex operation

●

Statistics counter registers for RMON/MIB

●

Interrupt generation to signal receive and transmit completion

●

Automatic pad and CRC generation on transmitted frames

●

Automatic discard of frames received with errors

●

Address checking logic supports up to four specific 48-bit addresses

●

Supports promiscuous mode where all valid received frames are copied to memory

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