ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR

7

ICS83031AMI REV. C OCTOBER 31, 2008

Parameter Measurement Information, continued

Propagation Delay

Output Duty Cycle/Pulse Width/Period

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

R2/R1 = 0.609.

Figure 1. Single-Ended Signal Driving Differential Input

nCLK

Q0

CLK

t

PD

V

DD

2

t

PERIOD

t

PW

t

PERIOD

odc =

V

DD

2

x 100%

t

PW

Q0

V_REF

Single Ended Clock Input

CLK

nCLK

R1

1K

C1

0.1u

R2

1K