ICS83021I datasheet(8/12 Pages) IDT

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ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both signals must meet the VPP and

VCMR input requirements. Figures 2A to 2F show interface

examples for the HiPerClockS CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

examples only. Please consult with the vendor of the driver

component to confirm the driver termination requirements. For

example, in Figure 2A, the input termination applies for IDT

HiPerClockS open emitter LVHSTL drivers. If you are using an

LVHSTL driver from another vendor, use their termination

recommendation.

Figure 2A. HiPerClockS CLK/nCLK Input

Driven by an IDT Open Emitter

HiPerClockS LVHSTL Driver

Figure 2C. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2E. HiPerClockS CLK/nCLK Input

Driven by a 3.3V HCSL Driver

Figure 2B. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVPECL Driver

Figure 2D. HiPerClockS CLK/nCLK Input

Driven by a 3.3V LVDS Driver

Figure 2F. HiPerClockS CLK/nCLK Input

Driven by a 2.5V SSTL Driver

1.8V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVHSTL

IDT

HiPerClockS

LVHSTL Driver

HiPerClockS

Input

125

3.3V

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

3.3V

LVPECL

HiPerClockS

Input

HCSL

*R3

*R4

CLK

nCLK

2.5V

3.3V

Zo = 50

Ω

Zo = 50

Ω

HiPerClockS

Input

*Optional – R3 and R4 can be 0

Ω

CLK

nCLK

HiPerClockS

Input

LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

100

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50

Ω

Zo = 50

Ω

CLK

nCLK

HiPerClockS

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

120

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