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STLUX385ATR Datenblatt(PDF) 58 Page - STMicroelectronics |
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STLUX385ATR Datenblatt(HTML) 58 Page - STMicroelectronics |
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58 / 99 page ![]() Option bytes STLUX385A 58/98 DocID024387 Rev 2 Bit 7:2: Rst_PWM[5:0] configures the PWM[n] reset value after the NRST signal 0: PWM[n] output low level (native default value) 1: PWM[n] output high level Note: The PWM signal programmed reset value is configured during the option byte loader phase, then before the NRST is released it assumes its proper initial values. nGENCFG (general configuration reg. protect.) nGENCFG: not(GENCFG) EMC byte protection MISCUOPT (miscellaneous config. reg.) Bit 0: WWdg_HALT window watchdog reset on Halt: 0: No reset generated on Halt if WWDG is active 1: Reset generated on Halt if WWDG is active Bit 1: WWdg_hw window watchdog hardware enable: 0: Window watchdog activation by SW 1: Window watchdog activation by HW Bit 2: IWdg_hw independent watchdog hardware enable: 0: Independent watchdog activation by SW 1: Independent watchdog activation by HW Offset: 0x004804 Default value: 0xFF 7 65432 1 0 Rst_PWM [5:0] nCOMP1_2 nEN_COLD_C FG r/w r/w r/w Offset: 0x004805 Default value: 0x28 (factory configuration) 7 654 32 1 0 RFU RFU RFU LSI_EN lWdg_hw WWdg_hw WWdg_HAL T r r r r/w r/w r/w r/w |
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