PCMB065T-2R2MS datasheet(17/22 Pages) IRF

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March 27, 2013 | V2.2 | PD97601

IR3473

6A Highly Integrated SupIRBuck

STABILITY CONSIDERATIONS

Constant‐on‐time control is a fast, ripple based control

scheme. Unstable operation can occur if certain conditions

are not met. The system instability is usually caused by:

Switching noise coupled to FB input:

This causes the PWM comparator to trigger prematurely

after the 500ns minimum on‐time for lower MOSFET.

It will result in double or multiple pulses every switching

cycle instead of the expected single pulse. Double pulsing

can causes higher output voltage ripple, but in most

application it will not affect operation. This can usually be

prevented by careful layout of the ground plane and the

FB sensing trace.

Steady state ripple on FB pin being too small:

The PWM comparator in IR3473 requires minimum

7mVp‐p ripple voltage to operate stably. Not enough ripple

will result in similar double pulsing issue described above.

Solving this may require using output capacitors with

higher ESR.

ESR loop instability:

The stability criteria of constant on‐time is:

If ESR is too small that this criteria is violated then sub‐

harmonic oscillation will occur. This is similar to the

instability problem of peak‐current‐mode control with

D>0.5. Increasing ESR is the most effective way to stabilize

the system, but the tradeoff is the larger output voltage

ripple.

System with all ceramic output capacitors:

For applications with all ceramic output capacitors, the ESR

is usually too small to meet the stability criteria. In these

applications, external slope compensation is necessary to

make the loop stable. The ramp injection circuit, composed

of R6, C13, and C14, shown in Figure 4 is required.

The inductor current ripple sensed by R6 and C13 is AC

coupled to the FB pin through C14. C14 is usually chosen

between 1 to 10nF, and C13 between 10 to 100nF. R6

should then be chosen such that L/DCR = C13*R6.

LAYOUT RECOMMENDATIONS

Bypass Capacitor:

As VCC bypass capacitor, a 1µF high quality ceramic

capacitor should be placed on the same side as the IR3473

and connected to VCC and PGND pins directly. A 1µF

ceramic capacitor should be connected from 3VCBP to

GND to avoid noise coupling into controller circuits. For

single‐ground designs, a resistor (R12) in the range of 5 to

10Ω in series with the 1µF capacitor as shown in Figure 4 is

recommended.

Boot Circuit:

CBOOT should be placed near the BOOT and PHASE pins to

reduce the impedance when the upper MOSFET turns on.

Power Stage:

Figure 30 shows the current paths and their directions

for the on and off periods. The on time path has low

average DC current and high AC current. Therefore, it is

recommended to place the input ceramic capacitor, upper,

and lower MOSFET in a tight loop as shown in Figure 30.

The purpose of the tight loop from the input ceramic

capacitor is to suppress the high frequency (10MHz range)

switching noise and reduce Electromagnetic Interference

(EMI). If this path has high inductance, the circuit will

cause voltage spikes and ringing, and increase the

switching loss. The off time path has low AC and high

average DC current. Therefore, it should be laid out with

a tight loop and wide trace at both ends of the inductor.

Lowering the loop resistance reduces the power loss. The

typical resistance value of 1‐ounce copper thickness is

0.5mΩ per square inch.

Figure 30: Current Path of Power Stage

OUT

ESR

⋅

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