USB4624 datasheet(31/68 Pages) SMSC

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USB 2.0 HSIC Hi-Speed 4-Port Hub Controller

Datasheet

SMSC USB4624

Revision 1.0 (06-17-13)

DATASHEET

Chapter 7 Device Interfaces

The USB4624 provides multiple interfaces for configuration and external memory access. This chapter

details the various device interfaces and their usage.

Note: For information on device configuration, refer to Chapter 6, "Device Configuration," on page 27.

7.1

SPI Interface

The device is capable of code execution from an external SPI ROM. On power up, the firmware looks

for an external SPI flash device that contains a valid signature of 2DFU (device firmware upgrade)

beginning at address 0xFFFA. If a valid signature is found, then the external ROM is enabled and the

code execution begins at address 0x0000 in the external SPI device. If a valid signature is not found,

then execution continues from internal ROM. The following sections describe the interface options to

the external SPI ROM.

The SPI interface is always enabled after reset. It can be disabled by setting the SPI_DISABLE bit in

the UTIL_CONFIG1 register.

Note: For SPI timing information, refer to Section 9.5.7, "SPI Timing," on page 63.

7.1.1

Operation of the Hi-Speed Read Sequence

The SPI controller will automatically handle code reads going out to the SPI ROM address. When the

controller detects a read, the controller drives SPI_CE_N low, and outputs 0x0B, followed by the 24-

bit address. The SPI controller outputs a DUMMY byte. The next eight clocks will clock-in the first byte.

When the first byte is clocked-in, a ready signal is sent back to the processor, and the processor gets

one byte.

After the processor gets the first byte, its address will change. If the address is one more than the last

address, the SPI controller will clock out one more byte. If the address is anything other than one more

than the last address, the SPI controller will terminate the transaction by driving SPI_CE_N high. As

long as the addresses are sequential, the SPI Controller will continue clocking data in.

Figure 7.1 SPI Hi-Speed Read Sequence

SPI_CE_N

SPI_CLK

SPI_DO

SPI_DI

MSB

HIGH IMPEDANCE

15 16

12 3 4

DOUT

ADD.

23 24

ADD.

39 40

31 32

47 48

55 56

63 64

71 72

DOUT

NN+1

DOUT

N+2

DOUT

N+3

DOUT

N+4

MSB

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