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HDLA-2416 Datenblatt(PDF) 9 Page - AVAGO TECHNOLOGIES LIMITED

Teilenummer HDLA-2416
Bauteilbeschribung  Four Character 5.0 mm (0.2 inch) Smart 5x7 Alphanumeric Displays
PDF  12 Pages
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Hersteller  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

HDLA-2416 Datenblatt(HTML) 9 Page - AVAGO TECHNOLOGIES LIMITED

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9
Display Clear
Data stored in the Character RAM, Control Register, and
Attribute RAM will be cleared if the clear (CLR) is held
low for a minimum of 10 µs. Note that the display will be
cleared regardless of the state of the chip enables (CE1,
CE2). After the display is cleared, the ASCII code for a space
(20hex) is loaded into all character RAM locations and
00hex is loaded into all Attribute RAM/Control Register
memory locations.
Data Entry
Figure 2 shows a truth table for the HDLX-2416 display.
Setting the chip enables (CE1, CE2) to logic 0 and the
cursor select (CU) to logic 1 will enable ASCII data
loading. When cursor select (CU) is set to logic 0, data
will be loaded into the Control Register and Attribute
RAM. Address inputs A0-A1 are used to select the digit
location in the display. Data inputs D0-D6 are used to load
information into the display. Data will be latched into
the display on the rising edge of the WR signal. D0-D6,
A0-A1, CE1, CE2, and CU must be held stable during the
write cycle to ensure that correct data is stored into the
display. Data can be loaded into the display in any order.
Note that when A0 and A1 are logic 0, data is stored in the
right most display location.
CUE
BL
CLR
CE1
CE2
WR
CU
A1
A0
D6
D5
D4
D3
D2
D1
D0
Function
0
1
1
Display ASCII
1
1
1
Display Stored Cursor
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
Reset RAMs
Blank Display but do not reset
X
0
1
RAMS and Control Register
Extended
Intensity
Master
Digit
Digit
Write to Attribute RAM
0
0
0
Functions
Control
Blank
Blank
Cursor
and Control Register
Disable
Disable 0
0
0 =
000 = 100%*
0 =
Digit
Digit
DBDn = 0, Allows Digit n to be
0
0
1
Enable
001 = 60%
Display
Blank
Cursor
blanked
D1-D5
010 = 40%
ON
Disable 1
1
011 = 27%
DBDn = 1 Prevents Digit n from
X
X
1
0
0
0
1 =
100 = 17%
1 =
Digit
Digit
being blanked.
0
1
0
Disable
101 = 10%
Display
Blank
Cursor
D1-D5
110 = 7%
Blanked
Disable 2
2
DCn = 0 Removes cursor from
111 = 3%
Digit n
D0
Digiit
Digit
0
1
1
Always
Blank
Cursor
DCn = 1 Stores cursor at Digit n
Enabled
Disable 3
3
1
0
0
Digit 0 ASCII Data (Right Most Character)
1
0
1
Digit 1 ASCII Data
X
X
1
0
0
0
Write to Character RAM
1
1
0
Digit 2 ASCII Data
1
1
1
Digit 3 ASCII Data (Left Most Character)
1
X
X
X
X
1
X
1
X
X
X
X
X
X
X
X
X
X
X
No Change
X
X
1
Figure 2. Display truth table.
0 = Logic 0; 1 = Logic 1; X = Do Not Care; * 000 = 27% for HDLU-2416
Cursor
When cursor enable (CUE) is a logic 1, a cursor will be
displayed in all digit locations where a logic 1 has been
stored in the Digit Cursor memory in the Attribute RAM.
The cursor consists of all 35 dots ON at half brightness.
A flashing cursor can be displayed by pulsing CUE. When
CUE is a logic 0, the ASCII data stored in the Character
RAM will be displayed regardless of the Digit Cursor bits.
Blanking
Blanking of the display is controlled through the BL input,
the Control Register and Attribute RAM. The user can
achieve a variety of functions by using these controls
in different combinations, such as full hardware display
blank, software blank, blanking of individual characters,
and synchronized flashing of individual characters or
entire display (by strobing the blank input). All of these
blanking modes affect only the output drivers, main-
taining the contents and write capability of the internal
RAMs and Control Register, so that normal loading of
RAMs and Control Register can take place even with the
display blanked.



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