HDLA-2416 datasheet(10/12 Pages) AVAGO

10 / 12 page

Table 1. Current Requirements at Different Brightness Levels

Symbol

Brightness

25°C Typ.

25°C Max.

Max. over Temp.

Units

IDD(#)

100%

110

130

160

60%

40%

27%

17%

10%

Figure 3 shows how the Extended Function Disable

(bit D6 of the Control Register), Master Blank (bit D2 of

the Control Register), Digit Blank Disable (bit D1 of the

Attribute RAM), and BL input can be used to blank the

display.

When the Extended Function Disable is a logic 1, the

display can be blanked only with the BL input. When the

Extended Function Disable is a logic 0, the display can be

blanked through the BL input, the Master Blank, and the

Digit Blank Disable. The entire display will be blanked if

either the BL input is logic 0 or the Master Blank is logic

1, providing all Digit Blank Disable bits are logic 0. Those

digits with Digit Blank Disable bits a logic 1 will ignore

both blank signals and remain ON. The Digit Blank Disable

bits allow individual characters to be blanked or flashed

in synchronization with the BL input.

Figure 3. Display blanking truth table.

EFD

DBDn

Display Blanked by BL

Display ON

Display Blanked by BL. Individual characters

“ON” based on “1” being stored in DBDn

Display Blanked by MB

Display Blanked by MB. Individual characters

“ON” based on “1” being stored in DBDn

Display Blanked by BL

Display ON

Dimming

Dimming of the display is controlled through either the

BL input or the Control Register. A pulse width modulated

signal can be applied to the BL input to dim the display.

A three bit word in the Control Register generates an

internal pulse width modulated signal to dim the display.

The internal dimming feature is enabled only if the

Extended Function Disable is a logic 0.

Bits 3-5 in the Control Register provide internal brightness

control. These bits are interpreted as a three bit binary

code, with code (000) corresponding to the maximum

brightness and code (111) to the minimum brightness.

In addition to varying the display brightness, bits 3-5 also

vary the average value of IDD. IDD can be specified at any

brightness level as shown in Table 1.

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