ADSP-21486KSWZ-2AB datasheet(43/68 Pages) AD

43 / 68 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. B

Page 43 of 68

March 2013

Sample Rate Converter—Serial Input Port

The ASRC input signals are routed from the DAI_P20–1 pins

using the SRU. Therefore, the timing specifications provided in

Table 41 are valid at the DAI_P20–1 pins.

Table 41. ASRC, Serial Input Port

Parameter

Min

Max

Unit

Timing Requirements

tSRCSFS

Frame Sync Setup Before Serial Clock Rising Edge

tSRCHFS

Frame Sync Hold After Serial Clock Rising Edge

5.5

tSRCSD

Data Setup Before Serial Clock Rising Edge

tSRCHD

Data Hold After Serial Clock Rising Edge

5.5

tSRCCLKW

Clock Width

(tPCLK × 4) ÷ 2 – 1

tSRCCLK

Clock Period

tPCLK × 4

1 The serial clock, data, and frame sync signals can come from any of the DAI pins. The serial clock and frame sync signals can also come via PCG or SPORTs. PCG’s input

can be either CLKIN or any of the DAI pins.

Figure 27. ASRC Serial Input Port Timing

DAI_P20–1

(SCLK)

SAMPLE EDGE

DAI_P20–1

(FS)

DAI_P20–1

(SDATA)

tSRCCLK

tSRCCLKW

tSRCSFS

tSRCHFS

tSRCHD

tSRCSD

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