MPC8349EVVALDB datasheet(51/87 Pages) FREESCALE

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

IPIC

15.2

GPIO AC Timing Specifications

Table 50 provides the GPIO input and output AC timing specifications.

16 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins.

16.1

IPIC DC Electrical Characteristics

Table 51 provides the DC electrical characteristics for the external interrupt pins.

16.2

IPIC AC Timing Specifications

Table 52 provides the IPIC input and output AC timing specifications.

Table 50. GPIO Input AC Timing Specifications1

Parameter

Symbol2

Min

Unit

GPIO inputs—minimum pulse width

tPIWID

Notes:

1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN.

Timings are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external

synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation.

Table 51. IPIC DC Electrical Characteristics1

Parameter

Symbol

Condition

Min

Max

Unit

Notes

Input high voltage

VIH

—2.0

OVDD +0.3

—

Input low voltage

VIL

—–0.3

0.8

—

Input current

IIN

——

±5

μA—

Output low voltage

VOL

IOL = 8.0 mA

—

0.5

Output low voltage

VOL

IOL = 3.2 mA

—

0.4

Notes:

1. This table applies for pins IRQ[0:7], IRQ_OUT, and MCP_OUT.

2. IRQ_OUT and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins.

Table 52. IPIC Input AC Timing Specifications1

Parameter

Symbol2

Min

Unit

IPIC inputs—minimum pulse width

tPICWID

Notes:

1. Input specifications are measured at the 50 percent level of the IPIC input signals. Timings are measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external

synchronous logic. IPIC inputs must be valid for at least tPICWID ns to ensure proper operation in edge triggered mode.

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