AM79C975VCW datasheet(260/304 Pages) AMD

260 / 304 page

260

Am79C973/Am79C975

P R E L I M INARY

SMIU Command Register (MReg Address 31)

Bit No.

Name and Description

7MIRQEN

Default: 0

Read/Write

MIRQEN allows the MIRQ pin to be active if

the interrupt flag MIRQ in the SMIU Interrupt

MIRQ pin will be disabled regardless of the

state of MIRQ. MRIRQEN is cleared by

H_RESET.

6MTX_DONEM

Default: 0

Read/Write

If MTX_DONEM is set to a 1, the MTX_DONE

bit in the SMIU Interrupt register will be

masked and unable to set the MIRQ bit.

MTX_DONEM is cleared by H_RESET.

5MRX_DONEM

Default: 0

Read/Write

If MRX_DONEM is set to a 1, the MRX_DONE

bit in the SMIU Interrupt register will be

masked and unable to set the MIRQ bit.

MRX_DONEM is cleared by H_RESET.

RESERVED

Default: 0

Read/Write as ZERO only

Reserved bit. For future use only

MLOOP

Default: 0

Read/Write

If MLOOP is set to 0, transmit frames will be

blocked from being received back, in case the

transceiver loops back the data. Setting

MLOOP to 1 enables loopback mode. All data

that is transmitted will be received back, if the

transceiver loop backs the data and the data

passes the acknowledgment frame filter. The

transceiver loopback can be achieved by pro-

gramming the device into loopback mode or by

using an external loopback connector. MLOOP

has no effect., when the Am79C975 controller

is configured for full-duplex operation. Re-

ceives are never blocked in full-duplex mode.

MLOOP is cleared by H_RESET.

2MRX_RPA

Default: 0

Read/Write

When MRX_RPA is set to a 1, the Am79C975

controller will accept runt frames (frames

shorter than 64 bytes) that pass the acknowl-

edgment frame filter. MRX_RPA is cleared by

H_RESET.

1:0

RESERVED

Default: 00

Read/Write as ZERO only

Reserved bits. For future use only

SMIU Interrupt Register (MReg Address 32)

Bit No.

Name and Description

7MIRQ

Default: 0

Read clear, write has no effect.

MIRQ indicates that one of the following inter-

rupt

causing

conditions

has

occurred:

MTX_DONE or MRX_DONE and the associat-

ed mask bit is programmed to allow the event

to cause an interrupt. If the MIRQEN bit in the

SMIU Command register is set to 1 and MIRQ

is set, the MIRQ pin will be active. MIRQ is

cleared by clearing all the active individual in-

terrupt bits that have not been masked out, i.e.

MIRQ will clear after reading the Interrupt reg-

ister. MIRQ is also cleared by H_RESET.

6MTX_DONE

Default: 0

Read clear, write has no effect.

MTX_DONE is set by the Am79C975 control-

ler after an alert frame has been transmitted.

When MTX_DONE is set, the MIRQ pin is as-

serted if MIRQEN is set to a 1 and the mask bit

MTX_DONEM in the SMIU Command register

is 0. MTIRQ is automatically cleared after

reading the Interrupt register. MTX_DONE is

also cleared by H_RESET.

5MRX_DONE

Default: 0

Read clear, write has no effect.

MRX_DONE is set by the Am79C975 control-

ler after an acknowledgment frame has been

received. When MRX_DONE is set, the MIRQ

pin is asserted if MIRQEN is set to a 1 and the

mask bit MRX_DONEM in the SMIU Com-

mand register is 0. MRX_DONE is automati-

cally

cleared

after

reading

the

Interrupt

H_RESET.

4:0

RESERVED

AM79C975VCW Datenblatt(PDF) 260 Page - Advanced Micro Devices

AM79C975VCW Datenblatt(HTML) 260 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL