AM79C975VCW datasheet(261/304 Pages) AMD

261 / 304 page

Am79C973/Am79C975

261

P R E L I M INARY

Default: 00000Read as ZERO only

Reserved bits. For future use only

SMIU Receive Pattern RAM Address Register

(MReg Address 33)

Bit No.

Name and Description

7:0

MRX_PADR

Default: 00h Read/Write

The SMIU Receive Pattern RAM Address reg-

ister contains the address of the location in the

Receive Pattern RAM where the next byte of

the Acknowledgment Frame Filter is written to.

The register is cleared to 0 by H_RESET and

every time the MRX_ENABLE bit is set to 1.

The address register autoincrements with ev-

ery byte write to the Receive Pattern RAM.

This allows a FIFO-type access to the Receive

Pattern RAM and the host does not need to

keep track of the location he is writing to. In ad-

dition, MRX_PADR can be set to any address

within the Receive Pattern RAM in order to

modify a specific location.

MIU Receive Pattern RAM Data Port (MReg Address

34)

Bit No.

Name and Description

7:0

MRX_PDATA

Default: undefined

Read/Write

This is the 8-bit data port used to write to the

Receive Pattern RAM.

SMIU Transmit Address Register (MReg Address

35)

Bit No.

Name and Description

7:0

MTX_ADR

Default: 00h Read/Write

The SMIU Transmit Address register contains

the address of the location in the Transmit

Data memory where the next byte of data is

written to. The register is cleared to 0 by

H_RESET and every time the MTX_START bit

in the Transmit Status register transitions is set

to 1. The address register auto-increments

with every byte written to the Transmit Data

memory. This allows a FIFO-type access to

the Transmit Data memory and the host does

not need to keep track of the location he is writ-

ing to. In addition, MTX_ADR can be set to any

address within the Transmit Data memory in

order to modify a specific location.

SMIU Transmit Data Port (MReg Address 36)

Bit No.

Name and Description

7:0

MTX_DATA

Default: undefined Write only, read has no ef-

fect.

This is the 8-bit data port used to write to the

Transmit Data memory.

SMIU Transmit Message Length Register (MReg

Address 37)

Bit No.

Name and Description

7:0

MTX_ LEN

Default: 00h Read/Write

The SMIU Transmit Message Length contains

the number of bytes from the Transmit Data

memory that will be transmitted by the

Am79C975 controller as the alert frame. The 4

bytes of FCS checksum are not part of the

memory content, but are calculated by the con-

troller and appended to the frame. The host is

responsible to load a valid value into the

Transmit Message Length register. Any value

below 60 will create a runt frame on the net-

work. Any value above 128 will create unpre-

dictable results.

SMIU Transmit Status Register (MReg Address 38)

Bit No.

Name and Description

7MTX_START

Default: 0

Read/Write

When MTX_START is set to a 1, the

Am79C975 controller will take the content of

the SMIU Transmit Data memory and transmit

the

data

the

frame.

Setting

MTX_START will also clear the Transmit Ad-

dress register. MTX_START is automatically

cleared

after

every

transmission.

MTX_START is cleared by H_RESET.

6:4

RESERVED

Default: 000 Read/Write as ZERO only

Reserved bits. For future use only

MTX_LCOL

Default: 0

Read only, write has no effect.

Transmit Late Collision indicates that during

the transmission of the alert frame a collision

has occurred after the first slot time has

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