ST8024LACDR datasheet(23/35 Pages) STMICROELECTRONICS

23 / 35 page

ST8024L

Functional description

Doc ID 17709 Rev 5

23/35

Figure 6.

Activation sequence at t3

6.7

Active mode

When the activation sequence is completed, the ST8024L is in its active mode. Data are

exchanged between the card and the microcontroller via the I/O lines.

The ST8024L is designed for cards without VPP (the voltage required to program or erase

the internal non-volatile memory).

6.8

Deactivation sequence

When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit

then executes an automatic deactivation sequence by counting the sequencer back and

finishing in the inactive mode (see Figure 7):

RST goes low (t10).

CLK is held low (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal

oscillator (approximately 25 µs).

I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T).

VCC starts to fall towards zero (t14 = t10 + 1.5 x T).

The deactivation sequence is complete at tDE, when VCC reaches its inactive state.

All card contacts become low impedance to GND; I/OUC, AUX1UC, and AUX2UC

remain at VDD (pulled-up via an 11 kΩ resistor).

The internal oscillator returns to its lower frequency.

ST8024LACDR Datenblatt(PDF) 23 Page - STMicroelectronics