EV1380 Datasheet Rev A

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6

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PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

AVIN

V

POK Current Sink

Capability

3.07V ≤ AVIN ≤ 3.53V

4

mA

VTT Tracking VDDQ

VDDQ – 2*VTT

VDDQ > 1V, VDDQ Rate of change

at 1V/ms

-25

+25

mV

Enable Pin Current

Tied to VDDQ through a 10k

Ω

50

μA

Logic Low Threshold

ENABLE, S_IN, VDDQOK

0.4

V

Logic High Threshold

ENABLE, S_IN, VDDQOK

1.8

V

S_OUT Low Level

0.4

V

S_OUT High Level

2.0

V

M/S Pin Logic Low

Threshold

Threshold voltage for Logic Low

0.4

V

M/S Pin Logic High

Threshold

Threshold voltage for Logic High

(internally pulled high; can be left

floating to achieve logic high)

2.0

2.7

V

M/S Pin Input Current

The ternary pin has 100k

Ω to

AGND and another 100k

Ω to an

internal 2.5V supply. If connecting

to AVIN recommend using a series

resistor. See Figure 7.

See

Figure

7.

μA

Current Balance

With 2 converters in parallel, the

difference between any two parts.

+/-10

%

Note 1

: Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.