Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

Preview PDF HTML

HM5259165B Datenblatt(PDF) 29 Page - Elpida Memory

Teilenummer HM5259165B
Bauteilbeschribung  512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
PDF  63 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5259165B Datenblatt(HTML) 29 Page - Elpida Memory

Back Button HM5259165B Datasheet HTML 25Page - Elpida Memory HM5259165B Datasheet HTML 26Page - Elpida Memory HM5259165B Datasheet HTML 27Page - Elpida Memory HM5259165B Datasheet HTML 28Page - Elpida Memory HM5259165B Datasheet HTML 29Page - Elpida Memory HM5259165B Datasheet HTML 30Page - Elpida Memory HM5259165B Datasheet HTML 31Page - Elpida Memory HM5259165B Datasheet HTML 32Page - Elpida Memory HM5259165B Datasheet HTML 33Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 29 / 63 page
background image
HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
29
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z
before data input.
READ to WRITE Command Interval (1)
CLK
Command
Dout
in B2
in B3
READ WRIT
in B0
in B1
High-Z
Din
CL=2
CL=3
DQM,
DQMU
/DQML
Burst Length = 4
Burst write
READ to WRITE Command Interval (2)
CLK
Command
Dout
READ
WRIT
Din
CL=2
CL=3
DQM,
DQMU/DQML
High-Z
2 clock
High-Z
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 cycle, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must
be set High so that the output buffer becomes High-Z before data input.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com