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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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LM4935RLEVAL Datenblatt(PDF) 21 Page - Texas Instruments |
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LM4935RLEVAL Datenblatt(HTML) 21 Page - Texas Instruments |
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21 / 91 page  MCL K I2S_CL K PCM_CL K PCM Interface I2S Interface Stereo DAC Mono ADC PLL % Q % R C B A From on chip 12 MHz oscillator USE_ONCHIP_OSC (to DET, PMC & SAR) LM4935, LM4935RLEVAL www.ti.com SNAS296D – OCTOBER 2005 – REVISED MARCH 2006 The LM4935 is designed to work from a 12.000 MHz or 11.025 MHz clock at point A. This is used to drive the power management and control logic. Performance may not meet the electrical specifications if the frequency at this point deviates significantly beyond this range. Figure 4-9. LM4935 Clock Network 4.2.4 COMMON CLOCK SETTINGS FOR THE DAC & ADC The DAC has an over sampling rate of 125 but requires a 250*fs clock at point B. This allows a simple clocking solution as it will work from 12.000 MHz (common in most systems with Bluetooth or USB) at 48 kHz exactly, the following table describes the clock required at point B for various clock sample rates in the different DAC modes: Table 4-4. Common DAC Clock Frequencies DAC Sample Rate (kHz) Clock Required at B (MHz) 8 2 11.025 2.75625 12 3 16 4 22.05 5.5125 24 6 32 8 44.1 11.025 48 12 The ADC has an over sampling ratio of 125 so the table below shows the required clock frequency at point C. Copyright © 2005–2006, Texas Instruments Incorporated Application Information 21 Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL |
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