6.0 Specification Changes

Specification Update

December 2008

22

6.0

Specification Changes

1.

Updates to Pull-Down Strapping resistor value

Issue:

The EX_ADDR[23:0] has a strong pull-up resistor attached internally. A 470 ohm

pull-down is required to override these pull-up resistors.

Line of Network Processors Hardware Design Guidelines and Intel® IXDP435 Multi-

2.

Updates to Pull-Down Resistor Value on JTG_TRST_N

Issue:

The JTG_TRST_N has a strong pull-up resistor attached internally. A 100 ohm

pull-down is required to override this pull-up resistor.

Line of Network Processors Hardware Design Guidelines and Intel® IXDP435 Multi-

3.

IEEE* 1588 Hardware Assistance Support

Issue:

The IEEE* 1588 standard defines a precision clock synchronization protocol for

Networked Measurement and Control Systems. It provides a kind of correction

mechanism by implementing several message exchange timing information to

of Network Processors provides hardware assist block to achieve this purpose. The

hardware assist block is called “Time Synchronization Hardware Assist” (TSYNC). Refer

The logic also supports one non-MII “auxiliary’ interface via GPIO[8:7] pins. The

GPIO[8:7] must be tied with a 10K-ohm pull-down while using the IEEE* 1588.

IXP43X Product Line of Network Processors Datasheet.

4.

Turbo-MII Mode Support

Issue:

Turbo MII (TMII) mode of operation. It is the standard MII supporting over clock up to

50 Mhz (instead of 25 Mhz) to provide throughput of 200 Mbps full-duplex. For details,

Datasheet.

5.

Add Procedure to Issue EMRS OCD Command during DDR SDRAM

Initialization

Issue:

JEDEC Standard for DDR2 SDRAM Specification, when OCD calibration is not used,

EMRS OCD Default command (A9=A8=A7=1) followed by EMRS OCD Calibration Mode

Exit command (A9=A8=A7=0) must be issued with other operating parameters of

EMRS.

Add the following procedures as step 16 in Section 11.2.2.10 DDR SDRAM Initialization

EMRS OCD Default command (A9=A8=A7=1) followed by EMRS OCD Calibration Mode

Exit command (A9=A8=A7=0) must be issued. The ‘OCD Program’ field is mapped to

DCALADDR register bit[9:7].

1) Configure the DCALCSR register (Hex offset: CC00 F500) with bit[2:0]=’011’

2) Configure the DCALADDR register (Hex offset: CC00 F504) with bit[1:0]=’01’, and

bit[9:7]=’111’ to issue a OCD Default command