December 2008

Specification Update

23

6.0 Specification Changes

3) Software must wait for at least 2 cycles. Then configure the DCALADDR register

(Hex offset: CC00 F504) with bit[1:0]=’01’, and bit[9:7]=’111’. (To issue a OCD Exit

command)

Note:

Other fields in the DCALCSR and DCALADDR registers should be left as ‘zero’ (default

value after reset). The ‘Qoff’, ‘RDQS’, and ‘DQS’ fields are mapped to DCALADDR

register bit[12:10] respectively.

The DLL enabled is configured through writing ‘0100’ to the SDIR register. The Rtt is

configured by writing to SDCR0 register bit[5:4].

Procedure to modify the bootloader (for EMRS OCD instruction):

Solution for Redboot* platform (packages/hal/arm/xscale/ixdp435/current/include/

hal_ixp425.h) as illustrated in Figure 2.

Solution for Redboot* platform (packages/hal/arm/xscale/ixdp435/current/include/

hal_platform_setup.h). Add in the EMRS code (bold) in between Step 14 and Step 15,

Figure 2.

Define DDR_DCALCSR and DDR_DCALADDR Registers

Figure 3.

EMRS Code Example

// Step 14. Issue mode register set w/o DLL reset

mov

r1, #DDR_SDIR_MODE_SET_NO_RESET

str

r1, [r0, #IXP_DDR_SDIR]

DELAY 0x100000, r1

//*********Added steps:EMRS OCD Calibration Default********

ldr

r2, [r0, #IXP_DDR_DCALADDR] //save DCALADDR value in r2 before modifying

ldr

r1, = 0x01000003

//set bit24=1 for SDRAM Enable

//set bits[0:1] for EMRS OCD Default

str

r1, [r0, #IXP_DDR_DCALCSR]

ldr

r1, =0x00000381

//set bits [9:7] and bit 0 for EMRS OCD Default

str

r1, [r0, #IXP_DDR_DCALADDR]

DELAY

0x100000, r1

//*********Added steps:EMRS OCD Calibration Mode Exit******

ldr

r1, =0x00000001

//set bit 0 only for exit

str

r1, [r0, #IXP_DDR_DCALADDR]

DELAY

0x100000, r1

str

r2, [r0, #IXP_DDR_DCALADDR] //restore original DCALADDR value

// Step 15. Start normal operation