Function Description

Power Supply

The ICS1660 is designed to be powered by a standard 9.0 volt

battery. The chip contains a voltage regulator that powers

external circuitry and provides the supply voltage for all digital

I/O on the circuit. This allows easy interface between the

ICS1660 and other standard logic working at 5.0V. This regu-

lator has short circuit protection and requires an external fil-

ter/compensation capacitor with a minimum value of 10uf.

In the event that an external regulated 5.0V supply is available,

to work from a common supply.

A low battery detection circuit is provided. This circuit is

designed for a typical trip point of 6.0V with hysteresis of about

200mV above the trip point. This signal is low active and is

multiplexed to the FSKBAT output pin when the PWR input is

low.

In an effort to keep power dissipation to a minimum and extend

battery life, most of the analog circuits are turned off when the

circuit is at rest waiting for a ring detect, (PWR pin low).

During this time only the regulator, low battery detect, refer-

ence generator, and ring detect circuits are active. When the

PWR pin is high, all circuits are active.

Ring Detect

As shown in the attached block diagram, the LINEA and

LINEB inputs should be connected to the telephone line

through external 82k

Ω resistors and 0.1uf capacitors. This

provides DC isolation and sets up a voltage divider with inter-

nal resistors that will detect 35.0V RMS typically. This voltage

is applied across the LINEA and LINEB inputs. The design

value of the internal resistors is 8.1K

Ω ± 20% with relative

accuracy of 2%. The RING output is high active.

Differential Front End

As shown in the attached block diagram, the LINEA and

LINEB inputs go into a differential amplifier which in turn

drives a filter. All resistors are internal to the chip while

capacitors are connected as shown in the block diagram. After

filtering, the signal is AC coupled into a high gain amplifier

that converts the signal to digital. This digital signal in turn acts

as the reference frequency for the phase comparator section of

the phase locked loop.

FSK Demodulation

After the signal from the telephone line has been filtered,

amplified and converted to digital, it acts as an input to a phase

locked loop. This PLL does FSK demodulation. The summing

amplifier shown in the block diagram provides a signal to the

VCO that should be about 0.5V for MARK frequency

(1200 HZ), and 2.0V for SPACE frequency (2200 HZ).

As shown in the block diagram, the LFILTER (loop filter)

output has a post filter attached to it. This POSTF signal is sent

to a comparator. The other side of the comparator is set to

approximately 2.5V. This comparator has a small amount

(200mV) of hysteresis and its output is the demodulated FSK

data. The FSK output is high for MARK frequency and low for

SPACE frequency. FSK data is multiplexed out of the

FSKBAT pin when the PWR input is high.

The VCO frequency is set with one external resistor with a

value in the range of 300K for a center frequency of 1700 HZ.

The lock range will be 660 HZ to 2630 HZ typical. The center

frequency reproducibility will be

±15%. The center frequency

can be adjusted in the system by connecting AMPIN to VSS,

PWR to VDD, and adjusting the external resistor for 1700 HZ.

This frequency can be observed at the LFILTER output or the

FSK/BAT output.

ICS1660

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