Input/Output Specifications

Digital

RING and FSKBAT outputs are standard CMOS outputs with

PWR is a logic input. A level converter circuit is on chip to

caused by through current in logic gates, the PWR input should

input signal is low when the ICS1660 is in lower power mode

waiting for an incoming call.

The LFILTER output is a standard CMOS output powered from

VDD. This output has an internal resistor with a typical value

of 30k

Ω. This is used in conjunction with the external capacitor

shown in the block diagram to form the loop filter for the PLL.

Analog

The value of the ring detect is as previously discussed 35.0V

RMS typical. The actual value is set by the choice of the

external resistors that are connected to the LINEA and LINEB

inputs. The matching of these resistors to the internal 8.1k

Ω

resistors is also a factor. The signal level at the chip that will

cause a ring is the bandgap voltage, (1.25V) or below.

The chip is designed for an input signal level of -12.5dbm to

-28.5dbm into 900 ohms. This translates to a signal that is

between 100 mV and 636 mV peak to peak.

The filter section should be connected as shown in the block

diagram. Using the external capacitors as shown, and assuming

nominal values on the internal resistors, the corner frequencies

are 900 HZ and 3860 HZ.

An external resistor with a value of approximately 330k

Ω is

connected between the LFILTER and POSTF pads. This resis-

tor along with the external capacitor shown in the block dia-

gram form the post filter. This post filter is used in conjunction

with the comparator to do the FSK demodulation.

Operation Temperature Range

. . . . . . . . . . . -55

°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . -50

°C to 150°C

*

Absolute maximum ratings are those values beyond which the safety of this device cannot be guaranteed.

These values are NOT RECOMMENDED operating conditions.

ICS1660

6