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ICS9176-01 Datenblatt(PDF) 5 Page - Integrated Circuit Systems |
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ICS9176-01 Datenblatt(HTML) 5 Page - Integrated Circuit Systems |
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5 / 8 page ![]() 5 ICS9176-01 AC Characteristics Notes: 1. Guaranteed by design and characterization. Not subject ot 100% test. 2. All skew specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V. 3. Duty cycle measured at 1.4V. 4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Clock Pulse Width 1 CLKW VDD=4.5V, fCLK=100 MHz 2.5 - 7.5 ns Output Rise time, 0.8 to 2.0V 1 tr 15pF load - 0.7 1 ns Rise time, 20% to 80% VDD 1 tr 15pF load - 1.5 2 ns Output Fall time, 2.0V to 0.8V 1 tf 15pF load - 0.7 1 ns Fall time, 80% to 20% VDD 1 tf 15pF load - 1.2 2 ns Output Duty cycle 1 dt 15pF load, Note 3 45 49/51 55 % Jitter, 1 sigma 1 Tls -60 - ps Jitter, absolute 1 Tabs -250 ±100 250 ps Input Frequency fi 20 - 100 MHz Output Frequency (Q outputs) fo For outputs >100 MHz, use Q/2 as feedback 20 - 120 MHz FBIN to IN skew 1 tskew1 Note 2, 4. Input rise time < 3ns -500 250 0 ps Skew between any 2 out- puts at same frequency 1 tskew2 Note 2, 4. -250 50 250 ps Skew between any 1 out put and Q/2 1 tskew3 Note 2, 4 -3 ±0.1 3 ns |
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