6

ICS9176-01

Applications

FBOUT is normally connected to FBIN to facilitate input to

output skew control. However, there is no requirement that

the external feedback connection be a direct hardwire from an

output pin to the FBIN pin. As long as the signal at FBIN is

derived directly from the FBOUT pin and maintains its fre-

quency, additional delays can be accommodated. The clock

phase of the outputs (rising edge) will be adjusted so that the

phase of FBIN and the input clock will be the same. See Figure

1 for an example.

Figure 1

In Figure 1, the propagation delay through the divide by 2

circuit is eliminated. The internal phase-locked loop will

adjust the output clock on the ICS9176-01 to ensure zero

phase delay between the FBIN and CLK signals, as a result,

the rising edge at the output of the divide by two circuit will be

aligned with the rising edge of the 66 MHz input clock. This

type of configuration can be used to eliminate propagation

delay as long as the signal at FBIN is continuous and is not

gated or conditional.

Figure 2

The ICS9176-01 is also ideal for clocking multi-processor

sys-tems. The 10 outputs can be used to synchronize the

operation of CPU cache and memory banks operating at

different speeds. Figure 2 depicts a 2-CPU system in which

processors and associated peripherals are operating at 66

MHz. Each of the nine outputs operating at 66 MHz are fully

utilized to drive the appropriate CPU, cache and memory control

logic. The 33 MHz output is used to synchronize the operation

of the slower memory bank to the restart of the system.