Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

AUGUST 1996

©1996 Integrated Device Technology, Inc.

DSC-3013/4

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

BiCMOS STATIC RAM

64K (8K x 8-BIT)

CACHE-TAG RAM

IDT71B74

FEATURES:

• High-speed address to MATCH comparison time

— Commercial: 8/10/12/15/20ns (max.)

• High-speed address access time

— Commercial: 8/10/12/15/20ns (max.)

• High-speed chip select access time

— Commercial: 6/7/8/10ns (max.)

• Power-ON Reset Capability

• Low power consumption

— 830mW (typ.) for 12ns parts

— 880mW (typ.) for 10ns parts

— 920mW (typ.) for 8ns parts

• Produced with advanced BiCMOS high-performance

technology

• Input and output directly TTL-compatible

• Standard 28-pin plastic DIP and 28-pin SOJ (300 mil)

DESCRIPTION:

The IDT71B74 is a high-speed cache address comparator

subsystem consisting of a 65,536-bit static RAM organized as

8K x 8 and an 8-bit comparator. A single IDT71B74 can map

8K cache words into a 2 megabyte address space by using the

21 bits of address organized with the 13 LSBs for the cache

address bits and the 8 higher bits for cache data bits. Two

IDT71B74s can be combined to provide 29 bits of address

comparison, etc. The IDT71B74 also provides a single RAM

clear control, which clears all words in the internal RAM to zero

when activated. This allows the tag bits for all locations to be

cleared at power-on or system-reset, a requirement for cache

comparator systems. The IDT71B74 can also be used as a

resettable 8K x 8 high-speed static RAM.

The IDT71B74 is fabricated using IDT’s high-performance,

high-reliability BiCMOS technology. Address access times as

fast as 8ns, chip select times of 6ns and address-to-match

times of 8ns are available.

The MATCH pin of several IDT71B74s can be wired-ORed

together to provide enabling or acknowledging signals to the

data cache or processor, thus eliminating logic delays and

increasing system throughput.

FUNCTIONAL BLOCK DIAGRAM

1

ADDRESS

DECODER

65,536-BIT

MEMORY ARRAY

I/O CONTROL

3013 drw 01

WE

GND

OE

CS

8

RESET

EQUAL

MATCH (OPEN DRAIN)

CONTROL

LOGIC

14.1