28F010

DESIGN CONSIDERATIONS

Two-Line Output Control

Flash-memories are often used in larger memory ar-

rays Intel provides two read-control inputs to ac-

commodate multiple memory connections Two-line

control provides for

a the lowest possible memory power dissipation

and

b complete assurance that output bus contention

will not occur

To efficiently use these two control inputs an ad-

dress-decoder output should drive chip-enable

while the system’s read signal controls all flash-

memories and other parallel memories This assures

that only enabled memory devices have active out-

puts while deselected devices maintain the low

power standby condition

Power Supply Decoupling

Flash-memory power-switching characteristics re-

quire careful device decoupling System designers

standby active and transient current peaks pro-

duced by falling and rising edges of chip-enable The

capacitive and inductive loads on the device outputs

determine the magnitudes of these peaks

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks

Each device should have a 01 mF ceramic capacitor

Place the high-frequency low-inherent-inductance

capacitors as close as possible to the devices Also

for every eight devices a 47 mF electrolytic capaci-

tor should be placed at the array’s power supply

tor will overcome voltage slumps caused by printed-

circuit-board trace inductance

and will supply

charge to the smaller capacitors as needed

Programming flash-memories while they reside in

the target system requires that the printed circuit

rent for programming Use similar trace widths and

Power UpDown Protection

The 28F010 is designed to offer protection against

accidental erasure or programming during power

transitions Upon power-up the 28F010 is indifferent

first Power supply sequencing is not required Inter-

nal circuitry in the 28F010 ensures that the com-

mand register is reset to the read mode on power

up

A system designer must guard against active writes

Since both WE

and CE

must be low for a com-

The control register architecture provides an added

level of protection since alteration of memory con-

tents only occurs after successful completion of the

two-step command sequences

28F010 Power Dissipation

When designing portable systems designers must

consider battery power consumption not only during

device operation but also for data retention during

system idle time Flash nonvolatility increases the

usable battery life of your system because the

28F010 does not consume any power to retain code

or data when the system is off Table 4 illustrates the

power dissipated when updating the 28F010

Operation

Notes

Power Dissipation

(Watt-Seconds)

Array ProgramProgram Verify

1

0171

Array EraseErase Verify

2

0136

One Complete Cycle

3

0478

NOTES

typical

Bytes)

4 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples from production lots

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