28F010 datasheet(2/30 Pages) INTEL

2 / 30 page

28F010

290207 – 1

Figure 1 28F010 Block Diagram

Table 1 Pin Description

Symbol

Type

Name and Function

A0–A16

INPUT

ADDRESS INPUTS

for memory addresses Addresses are internally

latched during a write cycle

DQ0–DQ7

INPUTOUTPUT

DATA INPUTOUTPUT

Inputs data during memory write cycles

outputs data during memory read cycles The data pins are active high

and float to tri-state OFF when the chip is deselected or the outputs

are disabled Data is internally latched during a write cycle

INPUT

CHIP ENABLE

Activates the device’s control logic input buffers

decoders and sense amplifiers CE

is active low CE

high

deselects the memory device and reduces power consumption to

standby levels

INPUT

OUTPUT ENABLE

Gates the devices output through the data buffers

during a read cycle OE

is active low

INPUT

WRITE ENABLE

Controls writes to the control register and the array

Write enable is active low Addresses are latched on the falling edge

and data is latched on the rising edge of the WE

pulse

Note

With VPP s 65V memory contents cannot be altered

VPP

ERASEPROGRAM POWER SUPPLY

for writing the command

VCC

DEVICE POWER SUPPLY

(5V g10%)

VSS

GROUND

NO INTERNAL CONNECTION

to device Pin may be driven or left

floating

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