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error amplifier. Similarly, the COMP pin is the error amplifier

output. These pins are used to compensate the voltage-mode

control feedback loop of the synchronous PWM converter.

VSEN1 (Pin 22)

This pin is connected to the PWM converter’s output voltage.

The PGOOD and OVP comparator circuits use this signal to

report output voltage status and for over- voltage protection.

DRIVE2 (Pin 1)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the AGP regulator’s pass transistor.

VSEN2 (Pin 10)

Connect this pin to the output of the AGP linear regulator.

The voltage at this pin is regulated to the level

predetermined by the logic-level status of the SELECT pin.

This pin is also monitored for under-voltage events.

SELECT (Pin 11)

This pin determines the output voltage of the AGP bus linear

regulator. A low TTL input sets the output voltage to 1.5V,

while a high input sets the output voltage to 3.3V.

DRIVE3 (Pin 18)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the 1.5V regulator’s pass transistor.

VSEN3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator.

This pin is monitored for under-voltage events.

DRIVE4 (Pin 15)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the 1.8V regulator’s pass transistor.

VSEN4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator.

This pin is monitored for undervoltage events.

Description

Operation

The HIP6021 monitors and precisely controls 4 output

voltage levels (Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic). It is

designed for microprocessor computer applications with

3.3V, 5V, and 12V bias input from an ATX power supply.

The IC has a synchronous PWM controller and three linear

controllers. The PWM controller (PWM) is designed to

controller drives 2 MOSFETs (Q1 and Q2) in a

synchronous-rectified buck converter configuration and

regulates the microprocessor core voltage to a level

programmed by the 5-bit digital-to-analog converter (DAC).

One of the linear controllers is designed to regulate the

digitally-programmable level of 1.5V or 3.3V. Selection of

either output voltage is achieved by applying the proper

logic level at the SELECT pin. The remaining two linear

designed to employ an external pass transistor.

Initialization

The HIP6021 automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input supply voltages. The POR monitors the

protection). The POR function initiates soft-start operation

after all supply voltages exceed their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially,

the voltage on the SS pin rapidly increases to approximately

1V (this minimizes the soft-start interval). Then an internal

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the SS pin to 4.5V. The PWM error amplifier reference input

(+ terminal) and output (COMP pin) are clamped to a level

proportional to the SS pin voltage. As the SS pin voltage

slews from 1V to 4V, the output clamp allows generation of

PHASE pulses of increasing width that charge the output

capacitor(s). After the output voltage increases to

approximately 70% of the set value, the reference input

clamp slows the output voltage rate-of-rise and provides a

smooth transition to the final set voltage. Additionally, all

linear regulators’ reference inputs are clamped to a voltage

proportional to the SS pin voltage. This method provides a

rapid and controlled output voltage rise.

Figure 3 shows the soft-start sequence for the typical

application. At T0 the SS voltage rapidly increases to

approximately 1V. At T1, the SS pin and error amplifier

output voltage reach the valley of the oscillator’s triangle

wave. The oscillator’s triangular wave form is compared to

the clamped error amplifier output voltage. As the SS pin

voltage increases, the pulse-width on the PHASE pin

increases. The interval of increasing pulse-width continues

until each output reaches sufficient voltage to transfer

control to the input reference clamp. If we consider the 2.5V

During the interval between T2 and T3, the error amplifier

reference ramps to the final value and the converter

regulates the output a voltage proportional to the SS pin

voltage. At T3 the input clamp voltage exceeds the

reference voltage and the output voltage is in regulation.

The remaining outputs are also programmed to follow the

SS pin voltage. The PGOOD signal toggles ‘high’ when all

output voltage levels have exceeded their under-voltage

levels. See the Soft-Start Interval section under

HIP6021