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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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HIP6021 Datenblatt(PDF) 12 Page - Intersil Corporation |
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HIP6021 Datenblatt(HTML) 12 Page - Intersil Corporation |
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12 / 15 page  2-307 Compensation Break Frequency Equations Figure 10 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 9. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 10 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS VOUT1 Q1 Q2 Q3 Q4 CSS +12V CVCC VIA CONNECTION TO GROUND PLANE ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER LOUT1 COUT1 CR1 HIP6021 CIN COUT2 VOUT2 VOUT3 +5VIN SS PGND LGATE1 UGATE1 PHASE1 DRIVE3 KEY GND VCC DRIVE2 OCSET1 ROCSET1 COCSET1 VOUT4 DRIVE4 +3.3VIN LIN Q5 COUT3 COUT4 +3.3VIN FIGURE 9. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT OSC REFERENCE LO CO ESR VIN ∆V OSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - DACOUT R1 R3 R2 C3 C2 C1 COMP VOUT FB ZFB HIP6021 ZIN COMP DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN F Z1 1 2 π R × 2C1 × ----------------------------------- = F Z2 1 2 π R1 R3 + () C3 × × ------------------------------------------------------- = F P1 1 2 π R 2 C1 C2 × C1 C2 + ---------------------- × × ------------------------------------------------------- = F P2 1 2 π R × 3C3 × ----------------------------------- = FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 100 80 60 40 20 0 -20 -40 -60 FP1 FZ2 10M 1M 100K 10K 1K 100 10 OPEN LOOP ERROR AMP GAIN FZ1 FP2 FLC FESR COMPENSATION FREQUENCY (Hz) GAIN MODULATOR GAIN CLOSED LOOP GAIN 20 V IN V PP ------------ log 20 R2 R1 -------- log HIP6021 |
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