HMP8115 datasheet(13/43 Pages) INTERSIL

13 / 43 page

If 16-bit YCbCr, 15-bit RGB data, or 16-bit RGB data is gen-

erated, it is output following the rising edge of CLK2 while

DVALID is asserted. Either linear or gamma-corrected RGB

data may be output. The pixel output timing is shown in Fig-

ures 12 to 15.

BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD

are output following the rising edge of CLK2. When BLANK

is asserted and VBIVALID is deasserted, the YCbCr outputs

have a value of 16 for Y and 128 for Cb and Cr; the RGB out-

puts have a value of 0.

NOTES:

11. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate

every cycle due to the 4:2:2 subsampling.

12. BLANK is asserted per Figure 9.

FIGURE 12. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

Cb0

CLK

DVALID

BLANK

P15-P8

P7-P0

tDVLD

Cr0

Cb2

Cr2

Cb4

NOTE:

13. BLANK is asserted per Figure 9.

FIGURE 13. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

CLK

DVALID

P15-P11

P10-P5

tDVLD

P4-P0

[P9-P5]

[P14-P10]

HMP8115

HMP8115 Datenblatt(PDF) 13 Page - Intersil Corporation