HMP8115 datasheet(21/43 Pages) INTERSIL

21 / 43 page

Host Interface

All internal registers may be written to or read by the host

processor at any time, except for those bits identiﬁed as

read-only. The bit descriptions of the control registers are

listed in Tables 9-48.

The HMP8115 supports the fast-mode (up to 400 kbps) I2C

interface consisting of the SDA and SCL pins. The device

acts as a slave for receiving and transmitting data over the

serial interface. When the interface is not active, SCL and

SDA must be pulled high using external 4k

Ω pull-up resis-

tors. The slave address for the HMP8115 is 88H.

Data is placed on the SDA line when the SCL line is low and

held stable when the SCL line is pulled high. Changing the

state of the SDA line while SCL is high will be interpreted as

either an I2C bus START or STOP condition as indicated by

Figure 20.

During I2C write cycles, the ﬁrst data byte after the slave

address is treated as the control register sub address and is

written into the internal address register. Any remaining data

bytes sent during an I2C write cycle are written to the control

registers, beginning with the register speciﬁed by the

address register as given in the ﬁrst byte. The address regis-

ter is then autoincremented after each additional data byte

sent on the I2C bus during a write cycle. Writes to reserved

bits within registers or reserved registers are ignored.

In order to perform a read from a speciﬁc control register

within the HMP8115, an I2C bus write must ﬁrst be per-

formed to properly setup the address register. Then an I2C

bus read can be performed to read from the desired control

cycle there are actually two START conditions as shown in

Figure 21. The address register is then autoincremented

after each byte read during the I2C read cycle. Reserved

registers return a value of 00H.

FIGURE 19. I2C TIMING DIAGRAM

SDA

SCL

tBUF

tLOW

tHIGH

tSU:DATA

tHD:DATA

tSU:STOP

SDA

SCL

START

CONDITION

1-7

ADDRESS

R/W

ACK

1-7

DATA

ACK

STOP

CONDITION

FIGURE 20. I2C SERIAL DATA FLOW

S = START CYCLE

P = STOP CYCLE

A = ACKNOWLEDGE

FROM MASTER

FROM HMP8115

0x88

DATA WRITE

DATA

0x88

DATA READ

NA = NO ACKNOWLEDGE

0x89

1000 1000 (R/W)

1000 1000

FIGURE 21. REGISTER WRITE/READ FLOW

CHIP ADDR

SUB ADDR

DATA

CHIP ADDR

SUB ADDR

CHIP ADDR

POINTED

TO BY

SUB ADDR

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

POINTED

TO BY

SUB ADDR

OPTIONAL FRAME

MAY BE REPEATED

n TIMES

HMP8115

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