UPD6376 datasheet(4/20 Pages) NEC

4 / 20 page

µPD6376

1. PIN FUNCTIONS

Pin No.

Symbol

Name

I/O

Function

4/8 fS SEL

Input

When this pin is Low or leaves Open, L-ch data and R-ch

data is input in time-division from Pin 15.

When this pin is High, L-ch data is input from Pin 15, and

R-ch data is input from Pin 14.

(Pulled down in IC with 100-k

Ω resistor)

D.GND

Digital GND

––

GND pin of logic block

Non Connection

––

Not connected to internal chip

D.VDD

Digital VDD

––

Power supply pin to logic block

A.GND

Analog GND

––

GND pin to analog block

R.OUT

R-ch OUTPUT

Output

Right analog signal output pin

A.VDD

Analog VDD

––

Power supply pin to analog block

A.VDD

Analog VDD

R.REF

R-ch Voltage Reference

––

Reference voltage pin. Normally connected to A. GND

L.REF

L-ch Voltage Reference

through via capacitor to lower impedance

L.OUT

L-ch OUTPUT

Output

Left analog signal output pin

A.GND

Analog GND

––

GND pin of analog block

LRCK/WDCK

Left/Right Clock

Input

When Pin 1 is Low or leaves Open:

WORD Clock

Functions as L-R judgment signal input pin.

When Pin 1 is High:

Functions as input data word judgment signal input pin.

LRSEL/RSI

Left/Right Selection

Input

When Pin 1 is Low or leaves Open:

R-ch Series Input

Functions as pin to select L-R polarity for LRCK signal.

When LRCK signal is High, set LRSEL pin to Low to input

L-ch data; When LRCK signal is LOW, set LRSEL pin to

High to input L-ch data.

When Pin 1 is High:

Functions as R-ch serial data input pin.

SI/LSI

Series Input

Input

When Pin 1 is Low or Open:

L-ch Series Input

Functions as L-ch and R-ch serial data input pin

alternately.

When Pin 1 is High:

Functions as L-ch serial data input pin.

CLK

CLOCK

Input

Input pin for read clock of serial input data

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