µPD6376

7

2.2 Supplying Clock to CLK only during Sample Data Interval

The analog outputs of the L.OUT and R.OUT pins are updated after the input of 4.5 clocks following data input.

(See 4. ELECTRICAL CHARACTERISTICS, Timing Charts 1 and 2.)

2.2.1 Inputting serial data (Pin 1 Low or Open)

Place the LRCK reverse timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-3)

and the next MSB input start time (Point B in Figure 2-3) (so as to include Points A and B).

Figure 2-3 Timing Chart of Serial Data Input

A

AB

B

1-sample data interval

LRCK reverse interval

LRCK reverse interval

LSB

CLK

SI

LRCK

16

12

34

12

34

5

6789 10 11 12 13 14 15 16

MSB

LSB

MSB

2.2.2 Inputting parallel data (Pin 1 High)

Place the WDCK falling edge timing between the falling edge of CLK at LSB input completion (Point A in Figure

2-4) and the next MSB input start time (Point B in Figure 2-4) (so as to include Points A and B).

Place the WDCK rising edge timing between the third falling edge of CLK from MSB input completion (Point C in

Figure 2-4) and the falling edge of CLK upon LSB input start (Point D in Figure 2-4) (so as to include Points C and

D).

Figure 2-4 Timing Chart of Parallel Data Input

A

AB

BC

D

WDCK falling

edge interval

WDCK falling

edge interval

WDCK rising edge interval

LSB

CLK

LSI

RSI

WDCK

16

12

34

12

5

6789 10 11 12 13 14 15 16

MSB

LSB

MSB

LSB

16

12

34

12

5

6789 10 11 12 13 14 15 16

MSB

LSB

MSB