PM0215 datasheet(47/91 Pages) STMICROELECTRONICS

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PM0215

The STM32 Cortex-M0 instruction set

Doc ID 022979 Rev 1

47/91

Incorrect examples

STM

R5!,{R4,R5,R6}

; Value stored for R5 is unpredictable

LDM

R2,{}

; There must be at least one register in the list

3.4.6

PUSH and POP

Push registers onto, and pop registers off a full-descending stack.

Syntax

PUSH reglist

POP reglist

where:

●

‘reglist’ is a non-empty list of registers (or register ranges), enclosed in braces.

Commas must separate register lists or ranges (see Examples on page 46).

Operation

●

PUSH stores registers on the stack, with the highest numbered register using the

highest memory address and the lowest numbered register using the lowest memory

address.

●

POP loads registers from the stack, with the lowest numbered register using the lowest

memory address and the highest numbered register using the highest memory

address.

●

PUSH uses the value in the SP register minus four as the highest memory address,

POP uses the SP register value as the lowest memory address, implementing a full-

descending stack. On completion, PUSH updates the SP register to point to the

location of the lowest store value, POP updates the SP register to point to the location

above the highest location loaded.

●

If a POP instruction includes PC in its reglist, a branch to this location is performed

when the POP instruction has completed. Bit[0] of the value read for the PC is used to

update the APSR T-bit. This bit must be 1 to ensure correct operation.

See LDM and STM on page 46 for more information.

Restrictions

In these instructions:

●

‘reglist’ must use only R0-R7. The exception is LR for a PUSH and PC for a POP.

Condition flags

These instructions do not change the flags.

Examples

PUSH {R0,R4-R7} ; Push R0,R4,R5,R6,R7 onto the stack

PUSH {R2,LR}

; Push R2 and the link-register onto the stack

POP

{R0,R6,PC} ; Pop r0,r6 and PC from the stack, then branch to new PC.

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