RM0319 datasheet(59/368 Pages) STMICROELECTRONICS

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RM0319

Multiport DDR controller (MPMC)

Doc ID 022640 Rev 3

59/368

The AHB port clock and the MPMC core clock must be aligned in frequency in phase. The

AHB-memory controller port interface block will not be required to perform any clock

synchronization in any of the FIFOs.

●

2:1 Port: Core Pseudo-Synchronous ('b10)

The port operates at half of the frequency of the core frequency, with clocks that are

aligned in phase. One stage of the two-stage synchronization logic of the FIFOs will be

utilized to synchronize commands, WRITE data and READ data to the appropriate

clock domain.

●

1:2 Port: Core Pseudo-Synchronous ('b01)

The port frequency is twice the core frequency, although the clocks are aligned in

phase. One stage of the two-stage synchronization logic of the FIFOs will be utilized to

synchronize commands, WRITE data and READ data to the appropriate clock domain.

●

Asynchronous ('b00)

The AHB bus and the memory controller core operate on clocks that are mismatched in

frequency and phase. The AHB port FIFOs use two stages of synchronization logic to

synchronize commands, WRITE data and READ data to the appropriate clock domain.

AHB Port FIFOs

Incoming transactions on the AHB bus are processed by the interface logic and mapped into

equivalent transactions on the memory controller core bus. These transactions are queued

in the port FIFOs.

There are three separate AHB port FIFOs for commands, READ data and WRITE data. The

depths of the FIFOs are configured by the user and generally dependent on system

requirements.

Command FIFO

The command FIFO holds the AHB command address, burst type and size. Typically, the

command FIFO is fairly small in depth due to the single-threaded, pipelined nature of the

AHB protocol. The protocol does not allow more than one outstanding transaction on any

AHB port. A deeper command FIFO is only useful in situations when the master issues

several very short WRITE bursts.

In this case, the commands and the associated data will be completely captured in the

command and write FIFOs and the bus will be free to start other operations.

Read FIFO

The read FIFO holds the ahbX_HRDATA signals sent back from the memory controller.

There is only one streaming READ data interface out from the memory for all AHB ports.

The memory controller steers this data stream to the port that requested the data. As a

result, the AHB ports must be ready to accept the READ data as soon as it is available on

the internal memory controller core bus to avoid stalling the memory controller itself.

Write FIFO

The write FIFO holds the ahbX_HWDATA signals sent into the memory controller. The depth

of the write FIFO depends on the typical length of a burst write transaction.

Note:

There is a WRITE data queue inside the memory controller core as well. Therefore, the

write FIFOs allow the AHB bus to off load its WRITE command completely before it is fully

transferred to the memory controller core buffers.

RM0319 Datenblatt(PDF) 59 Page - STMicroelectronics

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