LTC1277CS datasheet(13/20 Pages) LINER

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LTC1274/LTC1277

APPLICATI

I FOR ATIO

3V to keep the input span within the 5V supply in unipolar

mode. In bipolar mode the reference should be driven to

no more than 5V, the positive supply voltage of the chip.

Figure 6 shows an LT1006 op amp driving the Reference

pin. In unipolar mode, the reference can be driven up to

2.95V at which point it will provide a 0V to 5V input span.

For the bipolar mode, the reference can be driven up to 5V

at which point it will provide a

±4.23V input span. Figure

7 shows a typical reference, the LT1019A-2.5 connected

to the LTC1274. This will provide an improved drift (equal

to the maximum 5ppm/

°C of the LT1019A-2.5) and a

±2.115V (bipolar) or 4.231V (unipolar) full scale.

BOARD LAYOUT AND BYPASSING

Wire wrap boards are not recommended for high resolu-

tion or high speed A/D converters. To obtain the best

performance from the LTC1274/LTC1277, a printed cir-

cuit board is required. Layout for the printed circuit board

should ensure that digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital track alongside an analog

signal track or underneath the ADC. The analog input

should be screened by AGND.

High quality tantalum and ceramic bypass capacitors

should be used at the VDD and VREF pins as shown in

LTC1277 AIN

+/AIN– Input Settling

The input capacitor for the LTC1277 is switched onto the

AIN+ input during the sample phase. The voltage on the

AIN

+ input must settle completely within the sample

period. At the end of the sample phase the input capacitor

switches to the AIN– input and the conversion starts.

During the conversion the AIN

+ input voltage is effec-

tively “held” by the sample-and-hold and will not affect

the conversion result. It is critical that the AIN– input

voltage be free of noise and settles completely during the

conversion.

Internal Reference

The ADCs have an on-chip, temperature compensated,

curvature corrected bandgap reference which is factory

trimmed to 2.42V. It is internally connected to the DAC and

is available at Pin 2 (LTC1274) or Pin 3 (LTC1277) to

provide up to 1mA current to an external load.

For minimum code transition noise the reference output

should be decoupled with a capacitor to filter wideband

noise from the reference (10

µF tantalum in parallel with a

0.1

µF ceramic).

The VREF pin can be driven with a DAC or other means to

provide input span adjustment. The VREF pin must be

driven to at least 2.45V to prevent conflict with the internal

reference. The reference should be driven to no more than

Figure 6. Driving the VREF with the LT1006 Op Amp

VREF(OUT) ≥ 2.45V

Ω

INPUT RANGE:

±0.846VREF(OUT)

IN BIPOLAR MODE

0 TO 1.69VREF(OUT) IN

UNIPOLAR MODE

–

LT1006

LTC1274

AIN

AGND

VREF

µF

LTC1274/77 • F06

Figure 7. Supplying a 2.5V Reference Voltage

to the LTC1274 with the LT1019A-2.5

Ω

INPUT RANGE:

±2.115V (±0.846 × VREF)

IN BIPOLAR AND

0V TO 4.231V (1.69VREF(OUT))

IN UNIPOLAR MODE

LTC1274

AIN

AGND

VREF

µF

LTC1274/77 • F07

LT1019A-2.5

VIN

GND

VOUT

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