LTC1625IGN datasheet(15/24 Pages) LINER

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LTC1625

then VSEC will droop. An external resistor divider from

VSEC to the FCB pin sets a minimum voltage VSEC(MIN):

SEC MIN

()

≅+









119

If VSEC drops below this level, the FCB voltage forces

continuous operation until VSEC is again above its

minimum.

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest amount of time

that the LTC1625 is capable of turning the top MOSFET on

and off again. It is determined by internal timing delays and

the amount of gate charge required to turn on the top

MOSFET. Low duty cycle applications may approach this

minimum on-time limit and care should be taken to ensure

that:

ON MIN

OUT

()

()( )

If the duty cycle falls below what can be accommodated by

the minimum on-time, the LTC1625 will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple current and ripple voltage will increase.

The minimum on-time for the LTC1625 is generally about

0.5

µs. However, as the peak sense voltage (IL(PEAK) •

RDS(ON)) decreases, the minimum on-time gradually

increases up to about 0.7

µs. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-time limit in this situation, a significant amount of

cycle skipping can occur with correspondingly larger

current and voltage ripple.

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power (

×100%). Per-

cent efficiency can be expressed as:

%Efficiency = 100% – (L1 + L2 + L3 + ...)

APPLICATIONS INFORMATION

F C

DELAY









=µ

()

When the voltage on RUN/SS reaches 1.4V the LTC1625

begins operating with a clamp on ITH at 0.8V. As the

voltage on RUN/SS increases to approximately 3.1V, the

clamp on ITH is raised until its full 2.4V range is restored.

This takes an additional 0.5s/

µF. During this time the load

current will be folded back to approximately 30mV/RDS(ON)

until the output reaches half of its final value.

Diode D1 in Figure 7 reduces the start delay while allowing

CSS to charge up slowly for the soft start function. This

diode and CSS can be deleted if soft start is not needed. The

RUN/SS pin has an internal 6V zener clamp (See Func-

tional Diagram).

3.3V

OR 5V

RUN/SS

CSS

1625 F07

RUN/SS

CSS

Figure 7. RUN/SS Pin Interfacing

FCB Pin Operation

When the FCB pin drops below its 1.19V threshold,

continuous synchronous operation is forced. In this case,

the top and bottom MOSFETs continue to be driven

regardless of the load on the main output. Burst Mode

operation is disabled and current reversal is allowed in the

inductor.

In addition to providing a logic input to force continuous

operation, the FCB pin provides a means to regulate a

flyback winding output. It can force continuous synchro-

nous operation when needed by the flyback winding,

regardless of the primary output load.

The secondary output voltage VSEC is normally set as

shown in Figure 5a by the turns ratio N of the transformer:

VSEC ≅ (N + 1)VOUT

However, if the controller goes into Burst Mode operation

and halts switching due to a light primary load current,

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