4

LTC1654

up to REFHI/2 and when this pin is tied to REFLO, the

output will swing up to REFHI. These pins should not be

left floating.

CLR (Pin 2): The Asynchronous Clear Input.

SCK (Pin 3): The TTL Level Input for the Serial Interface

Clock.

SDI (Pin 4): The TTL Level Input for the Serial Interface

Data. Data on the SDI pin is latched into the shift register

on the rising edge of the serial clock. The LTC1654 re-

quires a 24-bit word. The first 8 bits are control/address

followed by 16 data bits. The last two of the 16 data bits are

don’t cares. If daisy-chaining is desired, then a 32-bit data

word can be used with the first 8 being don’t cares and the

following 24 bits as above.

CS/LD (Pin 5): The TTL Level Input for the Serial Interface

Enable and Load Control. When CS/LD is low, the SCK

signal is enabled, so the data can be clocked in. When

CS/LD is pulled high, the control/address bits are

decoded.

DGND/AGND (Pins 6, 12): Digital and Analog Grounds.

SDO (Pin 7): The output of the shift register that becomes

valid on the rising edge of the serial clock.

REFHI A/B (Pins 10, 14): The Reference High Inputs of the

LTC1654. There is a gain of 1 from this pin to the output

in a gain of 1 configuration. In a gain of 1/2 configuration,

REFLO A/B (Pins 11, 13): The Reference Low Inputs of the

LTC1654.

Requires a 0.1

µF bypass capacitor to ground.

1654 TD01

B0

C3

C3

X

X

X

CURRENT WORD

XX

X

X

XX

SCK

CS/LD

SDI

SDO

(PREVIOUS

WORD)

TI I G DIAGRA S

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).

See Applications Information.

Note 3: 100pF Load Capacitor

Note 4: DAC switched between code 200 and code 16383.

Note 6: Guaranteed by design.

when output is unloaded. See Applications Information.

PI FU CTIO S

ELECTRICAL CHARACTERISTICS