AFBR-79EBPZ datasheet(3/19 Pages) AVAGO

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High Speed Electrical Signal Interface

Figure 2 shows the interface between an ASIC/SerDes and

the QSFP+ module. For simplicity, only two electrical chan-

nels and one optical channel is shown. The high speed

signal lines are AC-coupled 100 Ohm differential lines. The

AC coupling is inside the QSFP+ module and not required

on the host board. The 100 Ohm differential terminations

are inside the QSFP+ module for the transmitter lines and

at the host ASIC/SerDes for the Receiver lines. All transmit-

ter and receiver electrical channels are compliant to mod-

ule XLPPI specifications per IEEE 802.3ba.

Control Signal Interface

The module has the following low speed signals for con-

trol and status: ModSelL, LPMode, ResetL, ModPrsL, IntL.

In addition, there is an industry standard two wire serial

interface scaled for 3.3 volt LVTTL. It is implemented as a

slave device. Signal and timing characteristics are further

defined in the Control Interface section. The registers of

the serial interface memory are defined in the Memory

Map section and the corresponding Avago Technologies

QSFP+ Memory Map document.

Regulatory & Compliance Issues

Various standard and regulations apply to the modules.

These include eye-safety, EMC, ESD and RoHS. See the

Regulatory Section for details regarding these and com-

ponent recognition. Please note the transmitter module

is a Class 1M laser product – DO NOT VIEW RADIATION

DIRECTLY WITH OPTICAL INSTRUMENTS. See Regulatory

Compliance Table for details.

Package Outline

The module is designed to meet the package outline de-

fined in the QSFP+ SFF-8436 Specification. See the pack-

age outline and host board footprint figures (Figures 13

- 16) for details.

Handling

The transceiver module can be damaged by exposure to

current surges and over voltage events. Care should be

taken to restrict exposure to the conditions defined in the

Absolute Maximum Ratings. Wave soldering, reflow sol-

dering and/or aqueous wash process with the modules on

board are not recommended. Normal handling precau-

tions for electrostatic discharge sensitive devices should

be observed.

Each module is supplied with an inserted port plug for

protection of the optical ports. This plug should always be

in place whenever a fiber cable is not inserted.

The optical connector includes recessed elements that

are exposed whenever a cable or port plug is not inserted.

Prior to insertion of a fiber optic cable, it is recommended

that the cable end be cleaned to avoid contamination

from the cable plug. The port plug ensures the optics re-

mains clean and no additional cleaning should be needed.

In the event of contamination, standard LC port cleaning

method may be used.

Figure 2. Application Reference Diagram

Host Board

(Only 2 electrical channels/1 optical channel shown for simplicity)

ASIC (SerDes)

2:1

Mux

1:2

De -Mux

20G

R x

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