© 1995 Microchip Technology Inc.

DS70010I-page 3

AY0438

1.3

LCD

φ

LCD

φ can be driven by an external signal or by con-

necting a capacitor between LCD

φ and ground (GND),

which will enable the on-chip oscillator required to gen-

erate the backplane output voltage. Figure 5 shows the

relationship between capacitance value and output fre-

quency. Leaving the LCD

φ input unconnected is not

recommended. When driven by an external clock, the

backplane output is in phase with the input clock. When

cascading

two

AY0438

devices

(Figure 6

and

Figure 7), the backplane output can be generated

using a capacitor to GND on the first AY0438. This

backplane output can then be connected to the LCD

φ

input of the second AY0438. The backplane output of

the second device is then used to drive the backplane

of the LCD module.

FIGURE 5: OSCILLATOR FREQUENCY

GRAPH (TYPICAL @ 25

°C)

140

120

100

80

60

40

0

20

40

60

80

100

120

CL (pF)

FIGURE 6: CASCADING TWO AY0438 DEVICES

FIGURE 7: CASCADE TIMING DIAGRAM

32 Latches

Clock

Load

Data

1 to 32

32 Segment Drivers

LCD AC

Generator

32-bit Static Shift Register

32 Latches

Data

Backplane

output

32 Segment Drivers

LCD AC

Generator

32-bit Static Shift Register

out

Data

in

Outputs

Data

in

Clock

Load

Clock

Load

out

Backplane

output

LCD

Φ

LCD

Φ

33 to 64

Outputs

START

CLOCK

Data in

Data out

Load

1/f

64

1

63

SEG 64

SEG 2

SEG 1