AY0438

DS70010I-page 4

© 1995 Microchip Technology Inc.

1.4

General

In order to avoid any race conditions, the Data In and

Load signals should not be changed during a falling

edge of the Clock. Figure 4 and Figure 7 show a typical

timing diagram for a 32 segment and 64 segment LCD

module.

1.5

Interfacing to a LCD Module and

PIC16CXX Device

Figure 8 shows a typical layout of an AY0438 con-

nected to a LCD module and interfaced to a PIC16CXX

family device. Example 1 lists code used to program

the PIC16CXX device. This code was complied using

MPASM.

FIGURE 8: INTERFACING TO A LCD MODULE AND PIC16CXX DEVICE

EXAMPLE 1:

EXAMPLE CODE

;*************************************************************************

;This program shows an interface between a PIC16CXX device

;and the AY0438 LCD controller to control a 7 Segment

;4 digit LCD module.

;The PIC16CXX interface to the AY0438 Hardware:

;

;

PORTB bit 0 --> CLK

;

PORTB bit 1 --> DATA IN

;

PORTB bit 2 --> LOAD

;

;The LCD module is connected to the AY0438 as follows:

;

Most Significant digit

--> seg1 to seg7

;

3rd Significant digit

--> seg9 to seg15

;

2nd Significant digit

--> seg17 to seg 23

;

Least Significant digit --> seg25 to seg 31

;

PIC16CXX

AY0438

RB0

RB1

RB2

RB7

Clock

Data In

Load

SEG1

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG9-15

SEG19-23

SEG25-31

Backplane

SEG A

SEG F

SEG G

SEG E

SEG D

SEG C

SEG B

LCD

7

A

B

C

D

E

F G

Backplane

7

7

LCD

Φ